Andes Technology Corporation

Zhong-Ho Chen

Wei-Hao Chiao

Yu-Lin Hsiao

Tien-Yu Chang

Hsin Ming Chen

An integrated circuit and a method for executing a cache management operation are provided. The integrated circuit includes a master interface, a slave interface, and a link. The link is connected between the master interface and the slave interface, and the link includes an A-channel, a B-channel, a C-channel, a D-channel, and an E-channel. The A-channel is configured to transmit a cache management operation message of the master interface to the slave interface, and the cache management operation message is configured to manage data consistency between different data caches. The D-channel is configured to transmit a cache management operation acknowledgement message of the slave interface to the master interface.

Integrated circuit and method for executing cache management operation

An electronic system, a system diagnostic circuit, and an operation method thereof are provided. The system diagnostic circuit includes a data register circuit, an instruction register circuit, a diagnostic controller circuit, a control register circuit, and a detect circuit. The diagnostic controller circuit determines to transmit test data to the instruction register circuit or the data register circuit according to an operating state. The detect circuit update the control register circuit when the first test data transmitted to the data register circuit meets a predefined pattern.

Electronic system, system diagnostic circuit and operation method thereof

The method for decoding a serially transmitted signal including: sampling the serially transmitted signal to obtain a plurality of sampled values according to a sampling period; obtaining a period of the serially transmitted signal according to a transition status of the sampled values; calculating a plurality of phase values according to the period and the transition status of the sampled values; obtaining a plurality of boundaries according to the phase values; and outputting a decoded data according to the boundaries and the transition status.

Decoding apparatus and method for decoding a serially transmitted signal thereof

A microprocessor is provided, which includes a processor core and an instruction loop cache. The processor core provides a fetch address of an instruction stream. The fetch address includes a tag and an index. The instruction loop cache receives the fetch address from the processor core. The instruction loop cache includes a cache array and a tag storage. The cache array stores multiple cache entries. Each cache entry includes a tag identification (ID). The cache array outputs the tag ID of the cache entry indicated by the index of the fetch address. The tag storage stores multiple tag values and output the tag value indicated by the tag ID output by the cache array. The instruction loop cache determines whether a cache hit or a cache miss occurs based on a bitwise comparison between the tag of the fetch address and the tag value output by the tag storage.

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Taichung, Taiwan

Zhong-Ho Chen