Intel Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Zhong Guo

Joseph A Manzella

Robert J Munoz

Walter A Roper

Described embodiments process data packets received that include a source address and at least one destination address. If the destination address is stored in a memory of an I/O adapter, the received data packet is processed in accordance with bridging rules associated with each destination address stored in the I/O adapter memory. If the destination address is not stored in the I/O adapter memory, the I/O adapter sends a task message to a processor to determine whether the destination address is stored in an address table stored in a shared memory of the network processor. The I/O adapter memory has lower access latency than the address table. If the destination address is stored in the address table, the received data packet is processed in accordance with bridging rules stored in the address table and the bridging rules stored in the I/O adapter memory are updated.

Address learning and aging for network bridging in a network processor

An apparatus having a parser and a circuit is disclosed. The parser is configured to generate a source address, a destination address and information by parsing a packet received via one of a plurality of networks. The circuit is configured to search a plurality of memories in parallel during a single cycle of operation in the apparatus. The searching includes a plurality of lookups in the memories of a plurality of data sets associated with the source address, the destination address and the information, respectively. The circuit is also configured to bridge the packet between the networks in response to the data sets.

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Bethlehem, PA, United States of America

Zhong Guo