Cisco Technology, Inc.

Future Wei Technologies, Inc.

Zhiyuan Wang

Xinli Gu

Zhanglei Wang

Yufang Sun

Qi Wu

Pu Wang

Zhaobo Zhang

Hong-Shin Jun

Lisheng Wang

Qixin Li

Haoming Zong

Xiaoyi Su

Hongxia Fang

Xiang Wu

A method of testing a multi-core network processor comprises placing the multi-core network processor in an online environment. A test is performed on a core of the multi-core network processor when the core is idle, and the core is released from the test when it is completed and resumes processing data in the online environment. In another embodiment, a network processor comprises a computer readable instructions module and a processing core. The computer readable instructions module is configured to store test instructions, and the processing core is configured to operate in an online environment and execute the test instructions to test the processing core when the processing core is idle. In yet another embodiment, an apparatus comprises a multi-core network processor that is configured to execute test instructions to perform a test on a core of the multi-core network processor when the core is idle.

Network processor online logic test

A method for testing an integrated circuit having memory comprises performing a structural test on the integrated circuit using data obtained from operating the memory in a functional mode. In another embodiment, an integrated circuit comprises a memory mode selection module, a memory module, and an output selection module. The memory mode selection module is configured to receive a functional mode signal and a test mode signal, and selectively transmit either the functional mode signal or the test mode signal based on a state of a control signal. The memory module is configured to receive the signal from the memory mode selection module and store data corresponding to signal to memory cells. The output selection module is configured to receive the data from the memory cells, and transmit the data to downstream circuitry, which may use the data to perform a structural test, such as a logic built-in self-test.

Technique to operate memory in functional mode under LBIST test

A method of testing an interconnect between an electronic component and an external memory comprises receiving a data word having data bits and translating the data word into multiple cycles. The multiple cycles are transmitted through the interconnect to the external memory one after another such that a value of the data bit being transmitted is switched for each cycle. In another embodiment, an electronic component comprises an interface, a translation unit, and a test module. The translation module is configured to receive a burst from the external memory through the interface and is configured to translate the burst into a data word. The test module is configured to receive the data word from the translation module and is configured to compare the data word to a test pattern to detect an interconnect defect.

PRBS test memory interface considering DDR burst operation

An example method is provided and includes executing a functional test for an integrated circuit and observing a failure associated with the integrated circuit. The method also includes executing a functional scan mode in order to reproduce the failure associated with the integrated circuit. A functional state of the integrated circuit is locked when the failure occurs, and the functional state is subsequently recovered for a structure test for the integrated circuit. In more particular embodiments, particular states of the functional test are evaluated and compared against other states associated with a model circuit that did not experience any failure in order to identify a latest cycle of the integrated circuit that could trigger the failure and an earliest cycle of the integrated circuit that could observe the failure.

System and method for executing functional scanning in an integrated circuit environment

An example method is provided and includes collecting inputs for a circuit board under test; evaluating historical repair records using a neuron network; providing repair actions for the circuit board based on the historical repair records; and providing an output reflecting a particular component of the circuit board to be replaced or to be repaired, where the output is associated with a developed probability of successfully fixing an issue that was identified by the test. In more specific implementations, the inputs include fault syndromes and log files associated with the circuit board under test. Additionally, at least one of the inputs of the neuron network is a syndrome vector extracted from a failure log. In yet other instances, particular outputs having higher probabilities are selected as the repair actions. The neuron network can be weighted using diagnosis knowledge weights.

System and method for providing adaptive manufacturing diagnoses in a circuit board environment

A clock signal within an application-specific integrated circuit (ASIC) is characterized while operating a subsystem. Subsequently, also on the ASIC, a testing clock signal is generated, based on the characterization of the operative clock signal, for purposes of testing the subsystem operating according to the testing clock signal instead of the clock signal. The ASIC includes a clock signal characterization circuit configured to characterize a clock signal within the ASIC; a programmable testing clock signal generator configured for being programmed based on said characterization of the clock signal, and for generating a test clock signal based on its said programming; and the subsystem tested when operating according to the testing clock signal instead of the clock signal.

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Fremont, CA, United States of America

Zhiyuan Wang