Omnivision Technologies, Inc.

Zhiyong Zhan

Rui Wang

Xin Ru Wang

Liang Zuo

Min Qu

Qingfei Chen

Kenny Geng

Hiroaki Ebihara

Zhe Gao

Qingwei Shan

Wei Wei Wang

Xuelian Liu

Tongtong Yu

Duli Mao

Yin Qian

Tiejun Dai

Dajiang Yang

Keiji Mabuchi

Zheng Yang

Chen-Wei Lu

Ling Fu

Wei Deng

Wanqing Xin

Qing Qin

Chin-Chang Pai

A pixel circuit includes a photodiode configured to photo generate image charge in response to incident light, a floating diffusion coupled to receive the image charge from the photodiode, a transfer transistor coupled between the photodiode and the floating diffusion to transfer the image charge from the photodiode to the floating diffusion, a reset transistor coupled between a variable voltage source and the floating diffusion, wherein the reset transistor is configured to be switched in response to a reset control signal, and a lateral overflow integration capacitor (LOFIC) coupled between the variable voltage source and the floating diffusion. The variable voltage source is configured to output a high-voltage level during a high conversion gain (HCG) reset signal readout and an HCG image signal readout, and a mid-voltage level during a LOFIC image signal readout and a LOFIC reset signal readout.

CAPMID design in VRFD for HDR structure

A stacked image sensor includes a signal-processing circuitry layer, a pixel-array substrate, a heat-transport layer, and a thermal via. The signal-processing circuitry layer includes a conductive pad exposed on a circuitry-layer bottom surface of the signal-processing circuitry layer. The pixel-array substrate includes a pixel array and is disposed on a circuitry-layer top surface of the signal-processing circuitry layer. The circuitry-layer top surface is between the circuitry-layer bottom surface and the pixel-array substrate. The heat-transport layer is located between the signal-processing circuitry layer and the pixel-array substrate. The thermal via thermally couples the heat-transport layer to the conductive pad.

Stacked image sensor

An imaging device includes groupings of photodiodes having four photodiodes. A transfer transistor is between each photodiode and a floating diffusion. Each floating diffusion is coupled to up to two photodiodes per grouping at a time through transfer transistors. A buffer transistor is coupled to each floating diffusion. The buffer transistors may be in a first or second grouping of buffer transistors. A first bit line is coupled to up to two buffer transistors of the first grouping and a second bit line is coupled to up to two buffer transistors of the second grouping of buffer transistors at a time. A color filter array including a plurality of groupings of color filters is disposed over respective photodiodes of the photodiode array, wherein each grouping of color filters includes four color filters having a same color, wherein each grouping of color filters overlaps two groupings of photodiodes.

Image sensor with shifted color filter array pattern and bit line pairs

An imaging system includes a pixel array configured to generate image charge voltage signals in response to incident light received from an external scene. An infrared illumination source is deactivated during the capture of a first image of the external scene and activated during the capture of a second image of the external scene. An array of sample and hold circuits is coupled to the pixel array. Each sample and hold circuit is coupled to a respective pixel of the pixel array and includes first and second capacitors to store first and second image charge voltage signals of the captured first and second images, respectively. A column voltage domain differential amplifier is coupled to the first and second capacitors to determine a difference between the first and second image charge voltage signals to identify an object in a foreground of the external scene.

Image sensor with in-pixel background subtraction and motion detection

An image sensor includes a pixel array with active rows of pixel cells, a black level calibration row with black image data generation circuits coupled to generate black image data signals representative of an absence of the incident light, and a dummy row with black level clamping circuits coupled to receive a black sun reference voltage to clamp bitlines of the pixel array, and a black level calibration circuit coupled to receive the black sun reference voltage to generate a black sun calibration voltage. A black sun feedback circuit is coupled to generate the black sun reference voltage in response to the black sun calibration voltage and a black level sample reference, and a black level sampling circuit is coupled to the bitlines to sample the black image data signals to generate the black level sample reference received by the black sun feedback circuit.

Image sensor with frame level black level calibration

A test voltage sample and hold circuitry is disclosed in a readout circuitry of an image sensor. This circuitry samples a voltage at demand value based on a ramp voltage shared by the ADC comparators of the readout circuitry. The value of the sampled voltage is controlled by a control circuitry which is able to predict and calculate at what time a ramp generator may carry the demand voltage value. The sampled voltage is held by a hold capacitor during readout of one row and is accessed during the next row by the control circuitry as test data to drive a device under test (DUT) which may be any portion of the image sensor to be tested. Measured data out of the DUT is compared with expected data. Based on the result of the comparison, a signal indicates the pass or fail of the self-test concludes a self-test of the DUT.

Image sensor with voltage buffer for self-test

An image sensor includes a pixel array with rows and columns of pixels. Each row of the pixel array has a first end that is opposite a second end of each row of the pixel array. Control circuitry is coupled to the first end of each row of the pixel array to provide control signals to each row of the pixel array from the first end of each row of the pixel array. Far end driver circuitry coupled to the second end of each row of the pixel array to selectively further drive from the second end of each row of the pixel array the control signals provided by the control circuitry from the first end of each row of the pixel array. The control circuitry is further coupled to provide far end control signals to the far end driver circuitry.

Image sensor far end driver circuitry providing fast settling row control signals

A pixel cell includes a second photodiode laterally surrounding a first photodiode in semiconductor material. The first and second photodiodes are adapted to photogenerate image charge in response to incident light. A floating diffusion is disposed in the semiconductor material proximate to an outer perimeter of the second photodiode. A first transfer gate is disposed proximate to the semiconductor material over a first channel region between the first and second photodiodes. The first transfer gate is coupled to transfer the image charge from the first photodiode to the second photodiode. A second transfer gate is disposed proximate to the semiconductor material over a second channel region between the second photodiode and the floating diffusion. The second transfer gate is coupled to transfer the image charge from the second photodiode to the floating diffusion.

Pixel array with embedded split pixels for high dynamic range imaging

A photodiode is adapted to accumulate image charges in response to incident light. A transfer transistor is coupled between the photodiode and a floating diffusion to transfer the image charges from the photodiode to the floating diffusion. A transfer gate voltage controls the transmission of the image charges from a transfer receiving terminal of the transfer transistor to the floating diffusion. A reset transistor is coupled to supply a supply voltage to the floating diffusion. A source follower transistor is coupled to receive voltage of the floating diffusion from a gate terminal of the source follower and provide an amplified signal to a source terminal of the source follower. A row select transistor is coupled to enable the amplified signal from the SF source terminal and output the amplified signal to a bitline. A bitline enable transistor is coupled to link between the bitline and a bitline source node. The bitline source node is coupled to a blacksun voltage generator. A current source generator is coupled between the bitline source node and a ground. The current source generator provides adjustable current to the bitline source node through a bias transistor controlled by a bias control voltage.

Bitline settling improvement and FPN reduction by floating bitline during charge transfer

A pixel circuit includes a photodiode disposed in a semiconductor material to accumulate image charge in response to incident light directed into the photodiode, and a transfer transistor coupled to the photodiode. The circuit also includes a noise correction circuit coupled to receive a transfer control signal and the noise correction circuit is coupled to selectively enable or disable the transfer transistor from receiving the transfer control signal. A storage transistor is coupled to the transfer transistor, and the transfer transistor is coupled to selectively transfer the image charge accumulated in the photodiode to the storage transistor for storage in response to the transfer control signal if the transfer transistor is enabled to receive the transfer control signal.

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Fremont, CA, United States of America

Zhiyong Zhan