Intel Corporation

Zhiyong Ma

Xianghong Tong

Kevin X Zhang

Zhanping Chen

Madhav Datta

Kevin D Johnson

Walid M Hafez

Peter K Moon

Jun He

Thomas N Marieb

Sarvesh H Kulkarni

Matthew B Pedersen

Mark T Bohr

Christopher J Jezewski

Subhash M Joshi

Martin D Giles

Miriam Ruth Reshotko

Jose A Maiz

Simon Yang

Flavio Griggio

Doowon Suh

Dave Emory

Guanghai Xu

Hyuk Ju Ryu

Tzeun-luh Huang

Rahim Kasim

Hasan Faraby

Wen-Hsien Chuang

Ira Jewell

Shuai Zhao

Charles Peterson

Jennifer Huening

Christine A King

Michael Mckeag

Nikholas G Toledo

Martin Von Haartman

Prasoon Joshi

May Ling Oh

Pulsed beam prober systems, devices, and techniques are described herein related to providing a beam detection frequency that is less than a electrical test frequency. An electrical test signal at the electrical test frequency is provided to die under test. A pulsed beam is applied to the die such that the pulsed beam has packets of beam pulses or a frequency delta with respect to the electrical test frequency. The packets of beam pulses or the frequency delta elicits a detectable beam modulation in an imaging signal reflected from the die such that the imaging signal is modulated at a detection frequency less than the electrical test frequency.

Stroboscopic electron-beam signal image mapping

Techniques are disclosed for providing cladded metal interconnects. Given an interconnect trench, a barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first layer of a bilayer adhesion liner is selectively deposited on the barrier layer, and a second layer of the bilayer adhesion liner is selectively deposited on the first layer. An interconnect metal is deposited into the trench above the bilayer adhesion liner. Any excess interconnect metal is recessed to get the top surface of the interconnect metal to a proper plane. Recessing the excess interconnect metal may include recessing previously deposited excess adhesion liner and barrier layer materials. The exposed top surface of the interconnect metal in the trench is then capped with the bilayer adhesion liner materials to provide a cladded metal interconnect core. In some embodiments, the adhesion liner is a single layer adhesion liner.

Cladded metal interconnects

Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.

Methods of forming secured metal gate antifuse structures

A tamper resistant fuse design is generally presented. In this regard, an apparatus is introduced comprising a plurality of fuses in an integrated circuit device to store values and a plurality of resistors in parallel to the fuses, wherein each fuse includes a parallel resistor to provide a potential dissipation path around the fuse. Other embodiments are also described and claimed.

Tamper resistant fuse design

A semiconductor substrate having metal oxide semiconductor (MOS) devices, such as an integrated circuit die, is mechanically coupled to a stress structure to apply a stress that improves the performance of at least a portion of the MOS devices on the die.

Transistor performance enhancement using engineered strains

The present invention describes a method including providing a component, the component having a bond pad; forming a passivation layer over the component; forming a via in the passivation layer to uncover the bond pad; and forming an under bump metallurgy (UBM) over the passivation layer, in the via, and over the bond pad, in which the UBM includes an alloy of Aluminum and Magnesium. The present invention also describes an under bump metallurgy (UBM) that includes a lower layer, the lower layer including an alloy of Aluminum and Magnesium; and an upper layer located over the lower layer.

Under bump metallurgy for Lead-Tin bump over copper pad

The invention relates to a ball limiting metallurgy stack for an electrical device that contains a tin diffusion barrier and thermo-mechanical buffer layer disposed upon a refractory metal first layer. The multi-diffusion barrier layer stack resists tin migration toward the upper metallization of the device.

Thermo-mechanically robust C4 ball-limiting metallurgy to prevent failure due to die-package interaction and method of making same

Under bump metallurgy for lead-tin bump over copper pad

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Hillsboro, OR, United States of America

Zhiyong Ma