Inspur Suzhou Intelligent Technology Co., Ltd

Zhixin Ren

Chuang Zhang

Jiaheng Fan

Jie Sun

Ke Liu

Zhongxiang Sun

Min Wang

A method, system and device for analyzing an error rate of an MLC chip. The method includes selecting data blocks from the MLC chip, and performing erasing-writing operations to the data blocks; after the erasing-writing operations are completed, reading each of groups of the dual-bits corresponding to each of the first pages and the second pages of the data blocks, and determining the bit state of the each of groups of the dual-bits; counting up the first total quantity of all of the dual-bits corresponding to the target page in the target bit state representing that the data writing is erroneous, to obtain a first error rate of the target page in the target bit state; and counting up a second total quantity of all of the dual-bits corresponding to the data blocks in the target bit state.

Error rate analysis method, system and apparatus for MLC chip

Provided is a data query method, applied to a heterogeneous acceleration platform. The data query method includes: determining operators in a database management system, and accomplishing, in a parallel processor, functions corresponding to the operators (S); if an SQL query statement is received, converting, by using a CPU, the where clause in the SQL query statement into a data structure including a binary tree and a linked list (S); controlling the CPU to generate an operation code stream of the data structure according to node information (S); and performing, by using the parallel processor, a screening operation corresponding to the operation code stream on records in the database management system to obtain a query result conforming to the where clause (S).

Data query method and system, heterogeneous acceleration platform, and storage medium

An FPGA cloud platform acceleration resource allocates and coordinates accelerator card resources according to delays between a host of a user and FPGA accelerator cards deployed at various network segments. Upon an FPGA usage request of the user, allocating an FPGA accelerator card in an FPGA resource pool that has a minimum delay to the host. A cloud monitoring management platform obtains_transmission delays to a virtual machine network according to different geographic locations of various FPGA cards in the FPGA resource pool, and allocating a card having a minimum delay to each user. The cloud monitoring management platform prevents unauthorized users from accessing acceleration resources in the resource pool. The invention protects FPGA accelerator cards that are not authorized for users, and ensures that the card allocated to a user has a minimum network delay, thereby optimizing acceleration performance, and improving user experience.

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Suzhou, China

Zhixin Ren