Sandisk Technologies Inc.

Zhixin Cui

Yanli Zhang

Masatoshi Nishikawa

Kiyohiko Sakakibara

Hardwell Chibvongodze

Satoshi Shimizu

Rajdeep Gautam

Johann Alsmeier

Mitsuteru Mushiga

Raghuveer S Makala

James K Kai

Fei Zhou

Tong Zhang

Ken Oowada

Murshed Chowdhury

Hisakazu Otoi

Hiroyuki Ogawa

Tatsuya Hinoue

Akio Nishida

Tomohiro Kubo

Kenji Sugiura

Michimoto Kaminaga

Keigo Kitazawa

Hiroshi Minakata

Yoshiyuki Okura

Yan Li

Masaaki Higashitani

Steven Theodore Sprouse

Yao-Sheng Lee

Senaka Kanakamedala

Masanori Tsutsumi

Michiaki Sano

Shinsuke Yada

Kensuke Yamaguchi

Monica Titus

Keisuke Izumi

Hirofumi Tokita

Shunsuke Takuma

Yukihiro Sakotsubo

Ippei Yasuda

Nobuyuki Fujimura

Takashi Kudo

Masahiro Wada

Chih-Yu Lee

A memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a substrate, a memory opening vertically extending through the first alternating stack and having a tapered sidewall surface at a level of one of the first electrically conductive layers, and a memory opening fill structure located in the memory opening and comprising a vertical stack of memory elements and a vertical semiconductor channel. One of the first electrically conductive layers includes a taper-containing electrically conductive layer that is located at a level of the lateral protrusion of the memory opening and has a contoured sidewall having a tapered sidewall segment that is parallel to the tapered sidewall surface of the lateral protrusion.

Three-dimensional memory device including a dummy word line with tapered corner and method of making the same

A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.

Three-dimensional memory device with separated contact regions

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory opening fill structures vertically extending through the alternating stack in a memory array region, and an electrically conductive spacer extending vertically and electrically connecting a first drain-select-level electrically conductive layer to a second drain-select-level electrically conductive layer.

Three-dimensional memory device with a conductive drain-select-level spacer and methods for forming the same

Three-dimensional memory device with separated contact regions and methods for forming the same

A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory material layer. A vertical stack of insulating material portions can be provided at levels of the insulating layers to provide a laterally-undulating profile to the memory material layer. Alternatively, a combination of inner insulating spacers and outer insulating spacers can be employed to provide a laterally-undulating profile to the memory material layer.

Three-dimensional memory device including laterally-undulating memory material layers and methods for forming the same

A joint level dielectric material layer is formed over a first alternating stack of first insulating layers and first spacer material layers. A first memory opening is formed with a tapered sidewall of the joint level dielectric material layer. A second alternating stack of second insulating layers and second spacer material layers is formed over the joint level dielectric material layer. An inter-tier memory opening is formed, which includes a volume of an second memory opening that extends through the second alternating stack and a volume of the first memory opening. A memory film and a semiconductor channel are formed in the inter-tier memory opening with respective tapered portions overlying the tapered sidewall of the joint level dielectric material layer.

Multilevel memory stack structure with tapered inter-tier joint region and methods of making thereof

A three-dimensional memory device includes a source contact layer overlying a substrate, an alternating stack of insulating layers and electrically conductive layers located overlying the source contact layer, and a memory opening fill structure located within a memory opening extending through the alternating stack and the source contact layer. The memory opening fill structure includes a composite semiconductor channel and a memory film laterally surrounding the composite semiconductor channel. The composite semiconductor channel includes a pedestal channel portion having controlled distribution of n-type dopants that diffuse from the source contact layer with a lower diffusion rate provided by carbon doping and smaller grain sizes, or has arsenic doping providing limited diffusion into the vertical semiconductor channel. The vertical semiconductor channel has large grain sizes to provide high charge carrier mobility, and is free of or includes only a low concentration of carbon atoms and n-type dopants therein.

Three-dimensional memory device including a composite semiconductor channel and a horizontal source contact layer and method of making the same

Apparatuses and techniques are described for providing separate source regions in the substrate below a block of memory cells. The source regions can be separately driven by respective voltage drivers to provide benefits such as more uniform program and erase speeds and narrower threshold voltage distributions. In one approach, a single source region is provided and divided into multiple source regions by etching trenches and filling the trenches with an insulating material. Contacts to the source regions can include post-shaped contacts which extend through the block for each source region. In another approach, one or more planar contacts extend through the block for each source region. In another aspect, a program operation applies different voltages to the respective source regions during a verify test of a program operation.

Memory block with separately driven source regions to improve performance

A semiconductor die can include an alternating stack of insulating layers and electrically conductive layers located on a substrate, memory stack structures extending through the alternating stack, drain regions located at a first end of a respective one of the vertical semiconductor channels of a memory stack structure, and bit lines extending over the drain regions and electrically connected to a respective subset of the drain regions. At least of a subset of the bit lines includes bump-containing bit lines. Each of the bump-containing bit lines includes a line portion and a bump portion that protrudes upward from a top surface of the line portion by a bump height. Bit line contact via structures overlie the bit lines and contact a bump portion of a respective one of the bump-containing bit lines.

Three-dimensional memory device including bump-containing bit lines and methods for manufacturing the same

A first-tier structure includes a first vertically alternating sequence of first continuous insulating layers and first continuous sacrificial material layers and a first-tier retro-stepped dielectric material portion overlying first stepped surfaces of the first vertically alternating sequence. A second vertically alternating sequence of second continuous insulating layers and second continuous sacrificial material layers is formed over the first-tier structure. Retro-stepped dielectric material portions are formed in each of the first-tier structure and the second-tier structure. After formation of memory stack structures, electrically conductive layers replace portions of the first and second continuous sacrificial material layers. Laterally-isolated contact via structures can be formed through the second-tier structure and a first-tier retro-stepped dielectric material portion on first electrically conductive layers in the first-tier structure. Sacrificial landing pad structures can be employed to enable concurrent formation of contact via cavities through the retro-stepped dielectric material portions.

Through-stack contact via structures for a three-dimensional memory device and methods of forming the same

Multiple bonded units are provided, each of which includes a respective front-side die and a backside die. The two dies in each bonded unit may be a memory die and a logic die configured to control operation of memory elements in the memory die. Alternatively, the two dies may be memory dies. The multiple bonded units can be attached such that front-side external bonding pads have physically exposed surfaces that face upward and backside external bonding pads of each bonded unit have physically exposed surfaces that face downward. A first set of bonding wires can connect a respective pair of front-side external bonding pads, and a second set of bonding wires can connect a respective pair of backside external bonding pads.

Stacked die assembly including double-sided inter-die bonding connections and methods of forming the same

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Drain-select-level trenches through an upper subset of the sacrificial material layers, and backside trenches are formed through each layer of the alternating stack. Backside recesses are formed by removing the sacrificial material layers. A first electrically conductive material and a second electrically conductive material are sequentially deposited in the backside recesses and the drain-select-level trenches. Portions of the second electrically conductive material and the first electrically conductive material may be removed by at least one anisotropic etch process from the drain-select-level trenches to provide drain-select-level electrically conductive layers as multiple groups that are laterally spaced apart and electrically isolated from one another by cavities within the drain-select-level trenches.

Three-dimensional memory device including composite word lines and multi-strip select lines and method for making the same

Growing community of inventors

Nagoya, Japan

Zhixin Cui