Sony Semiconductor Solutions Corporation

Sony Corporation

Zhiwei Zhou

Takashi Masuda

Kenichi Maruko

Yosuke Ueno

Jeremy Chatwin

Yuki Seo

Yoshifumi Miyajima

An electronic circuit that includes a plurality of first drivers coupled in parallel, the first drivers each including transistors coupled in series and transmitting data at a predetermined communication speed, and a second driver that includes transistors coupled in series and transmitting data at a communication speed lower than the communication speed of the first driver. The number of first drivers operating in parallel is sufficient for output impedance of the first drivers to meet a predetermined standard through application of an electrical potential to bodies of the transistors of the first drivers. The electrical potential causes an output level of the second driver to meet a predetermined standard.

Electronic circuit and electronic apparatus

The operation range of a phase detector provided with a flip-flop is improved, and the jitter tolerance of a receiving circuit is enhanced. The phase detector includes a holding unit and a detection unit. In the phase detector, the holding unit holds an input signal in synchronization with a predetermined periodic signal. The detection unit detects a phase difference between a designated edge and the predetermined periodic signal on the basis of a signal held in the holding unit. The designated edge is designated by a control signal that designates one of a rising edge and a falling edge of the input signal as the designated edge.

Phase detector, phase synchronization circuit, and method of controlling phase synchronization circuit

There is provided a reception unit, including: a transition detection section configured to detect a transition of an input data signal; an oscillation section configured to generate a clock signal and vary a phase of the clock signal based on a result of detection made by the transition detection section, the clock signal having a frequency in accordance with a first control signal; a first sampling section configured to sample the input data signal based on the clock signal and thereby generate an output data signal; and a control section configured to generate the first control signal based on the input data signal, the output data signal, and the clock signal.

Reception unit and receiving method

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Tokyo, Japan

Zhiwei Zhou