Huawei Technologies Co., Limited

Zhiwei Shang

Yin Tan

Haohao Liao

Zhijun Mo

Tongyu Ge

Luyun Lin

The present disclosure relates to one or more processors, communicative with one or more computer-readable media, are configured to automatically generate a sensitive text detector including a regular expression or keyword. A set of text inputs, including sensitive text, are received. The sensitive text is extracted from the set of text inputs. Based on the extracted sensitive text, one or both of the regular expression and the keyword are generated. The generated regular expression and/or keyword are used to generate a sensitive text detector for sensitive text detection.

Methods and devices for generating sensitive text detectors

A low latency relinearization process can be performed in an FPGA cluster for accelerating homomorphic encryption. The low-latency process performs an early calculation of matrix rows to make the summation result available earlier in the relinearization to reduce waiting of subsequent operations.

Low-latency pipeline and method for use of a low latency pipeline in homomorphic encryption

The present disclosure describes a method, an apparatus, and a non-transitory computer-readable medium for detecting sensitive text information such as privacy-related text information from a signal and modifying the signal by removing the detected sensitive text information therefrom. The apparatus receives the signal such as an image, a video clip, or an audio clip, and recognizes a text string therefrom. The apparatus then detects, from the text string, a substring based on a similarity between the substring and a regular expression, and modifies the signal by removing information related to the detected substring from the signal.

Methods, apparatuses, and computer-readable storage media for image-based sensitive-text detection

A field-programmable gate array (FPGA) cluster, comprising a plurality of FPGA devices, can be used to accelerate homomorphic encryption functionality. In particular, the FPGA cluster can accelerate the relinearization process used in homomorphic encryption by using multiple FPGA devices to perform portions of the relinearization process in parallel. Further, the use of the FPGA cluster provides sufficient memory resources to allow data used by the relinearization process, namely the keyswitch keys, to be stored on-chip.

Field-programmable gate array (FPGA) clusters and methods of using an FPGA cluster for homomorphic encryption acceleration

Systems and memory devices are disclosed for fully homomorphic encryption (FHE). The system may include a processing unit including: a data memory for storing coefficients for a polynomial; a twiddle factor (TF) memory for storing TF values associated with the polynomial; a TF register connected to the TF memory; a plurality of first registers connected to the data memory; a plurality of first MUXs connected to the first registers; a plurality of second registers connected to the plurality of first MUXs; a plurality of Butterfly (BF) cores connected to the plurality of the second registers and the TF register; wherein each of the plurality of BF cores is configured to, responsive to a control signal, perform a Butterfly Transform (BFT) operation based on two coefficients from the data memory and a TF value from the TF memory.

Growing community of inventors

Waterloo, Canada

Zhiwei Shang