Broadcom Corporation

Zhiqing Zhuang

Vafa James Rakshani

Lawrence John Madar, Iii

Vinay Bhasin

Chenmin Zhang

Jalil Fadavi-Ardekani

Sam H Liu

Chaoyang Zhao

Soheyla Kamal, Legal Representative

Provided is a method for transferring data from one clock domain within a synchronizer to another domain within the synchronizer. The method includes determining system clock parameters within the synchronizer and analyzing a first domain clock signal based upon the system clock parameters. Next, a second domain clock signal is analyzed based upon the first domain clock signal and the system clock parameters. A determination is made as to when to transfer data from a first clock domain to a second clock domain in accordance with the analysis of the first and second domain clock signals, and an enable signal is provided to affect the data transfer from the first domain to the second clock domain.

Method and system for advance high performance bus synchronizer

A state machine and an external interface, including its associated input-outputs (IOs), are always powered on and used to manage the chip power modes and power mode transitions. The chip power modes are defined as RUN, HIBERNATE, POWERDOWN, with many more possible with this invention. For example, once the device is in HIBERNATE or POWERDOWN modes, the power supplies to the IC are either reduced, or completely disconnected except for this controller state machine. This invention's state machine and control mechanism, in response to some external 'wake up event', will bring the chip to RUN mode by managing the state of the external power supplies through its control interface. The implementation achieves small die size and extreme low power consumption.

Method for managing and controlling the low power modes for an integrated circuit device

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Irvine, CA, United States of America

Zhiqing Zhuang