Taiwan Semiconductor Manufacturing Comp. Ltd.

Zhiqiang Wu

Kuo-Cheng Ching

Chung-Wei Wu

Chih-Hao Wang

Wen-Hsing Hsieh

Ka-Hing Fung

Ken-Ichi Goto

Carlos H Diaz

Jean-Pierre Colinge

Tzer-Min Shen

Kuan-Lun Cheng

Chih-Sheng Chang

Jon-Hsu Ho

Chun-Fu Cheng

Chih-Ching Wang

Tsung-Hsing Yu

Yi-Ming Sheu

Chung-Cheng Wu

Wei-Hao Wu

Gwan Sin Chang

Chia-Wen Liu

Nuo Xu

Yu-Ming Lin

Wen-Yuan Chen

Kai-Chieh Yang

Wei Ju Lee

Ching-Fang Huang

Gwan-Sin Chang

Kuo-An Liu

Kai Tak Lam

Gaurav Gupta

Ching-Wei Tsai

Li-Jui Chen

Ya-Yun Cheng

Huan-Sheng Wei

Peng-Chun Liou

Yih Wang

Shang-Chieh Chien

Heng-Hsin Liu

Yi-Ching Liu

Min Cao

Tai-Yu Chen

Chieh Hsieh

Dhanyakumar Mahaveer Sathaiya

Chung-I Yang

Sagar Deepak Khivsara

Sai-Hooi Yeong

Kuo-Cheng Chiang

Shih-Chang Liu

Meng-Han Lin

Han-Jong Chia

Hung-Li Chiang

Ying-Keung Leung

Xiaomeng Chen

Yuan-Chen Sun

Chien-Hong Chen

Sheng-Kang Yu

Hua Feng Chen

Kuan-Ting Liu

Szu-Wei Huang

Yen-Tien Tung

Meng-Yu Lin

Yin-Chuan Chuang

Ting-Yun Wu

Yee-Chia Yeo

Chih-Hao Chang

Ta-Pen Guo

Chun-Chieh Lu

Chih-Pin Tsao

Hsiang Mei Chen

Shih-Syuan Huang

Jeffrey Junhao Xu

Yeh Hsu

Po-Sheng Lu

Cho-Ying Lin

Huang-Siang Lan

Chun Chung Su

Sathaiya Mahaveer Dhanyakumar

Yu-Chien Chiu

Mahaveer Sathaiya Dhanyakumar

Harry-Hak-Lay Chuang

Chi-Wen Liu

Shi Ning Ju

Chih Chieh Yeh

Ziwei Fang

Chao-Hsiung Wang

Dian-Hau Chen

William Joseph Gallagher

Chih-Chieh Yeh

Jeff J Xu

Yimin Huang

Tien-Wei Chiang

Chun-Hsiang Fan

Ming-Jie Huang

Chia-Hsiang Chen

Yuan-Yang Hsiao

Jiun-Jia Huang

Chen-Chiu Huang

Chia-En Huang

A device includes a substrate, a first semiconductor channel over the substrate, and a second semiconductor channel over the substrate and laterally separated from the first semiconductor channel. A gate structure covers and wraps around the first semiconductor channel and the second semiconductor channel. A first source/drain region abuts the first semiconductor channel on a first side of the gate structure, and a second source/drain region abuts the second semiconductor channel on the first side of the gate structure. An isolation structure is under and between the first source/drain region and the second source/drain region, and includes a first isolation region in contact with bottom surfaces of the first and second source/drain regions, and a second isolation region in contact with sidewalls of the first and second source/drain regions, and extending from a bottom surface of the first isolation region to upper surfaces of the first and second source/drain regions.

Field effect transistor with merged epitaxy backside cut and method

A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a fin, and a semiconductor layer. The fin is over the substrate, the semiconductor layer is over the fin, the substrate and the fin are made of different materials, and the fin and the semiconductor layer are made of different materials. The method includes forming a dielectric layer over the semiconductor layer and the fin. The method includes forming a semiconductor structure over a sidewall of the dielectric layer. The method includes removing a first top portion of the dielectric layer over a top surface of the semiconductor layer. The method includes forming a gate over the semiconductor layer, the dielectric layer, and the semiconductor structure.

Semiconductor device structure with fin and method for forming the same

Source/drain silicide that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a first channel layer disposed over a substrate, a second channel layer disposed over the first channel layer, and a gate stack that surrounds the first channel layer and the second channel layer. A source/drain feature disposed adjacent the first channel layer, second channel layer, and gate stack. The source/drain feature is disposed over first facets of the first channel layer and second facets of the second channel layer. The first facets and the second facets have a (111) crystallographic orientation. An inner spacer disposed between the gate stack and the source/drain feature and between the first channel layer and the second channel layer. A silicide feature is disposed over the source/drain feature where the silicide feature extends into the source/drain feature towards the substrate to a depth of the first channel layer.

Source/drain silicide for multigate device performance and method of fabricating thereof

A semiconductor structure includes a substrate and a semiconductor channel layer over the substrate. The semiconductor structure includes a high-k gate dielectric layer over the semiconductor channel layer, a work function metal layer over the high-k gate dielectric layer, and a bulk metal layer over the work function metal layer. The work function metal layer includes a first portion and a second portion over the first portion. Both the first portion and the second portion are conductive. Materials included in the second portion are also included in the first portion. The first portion is doped with silicon at a first dopant concentration, and the second portion is not doped with silicon or is doped with silicon at a second dopant concentration lower than the first dopant concentration.

Effective work function tuning via silicide induced interface dipole modulation for metal gates

A ferroelectric memory device includes a multi-layer stack, a ferroelectric layer, and channel layers. The multi-layer stack is disposed on a substrate and includes conductive layers and dielectric layers stacked alternately. The ferroelectric layer has a curvy profile and is disposed along sidewalls of the conducive layers and sidewalls of the dielectric layers. The channel layers are separated from each other and disposed on the ferroelectric layer, and correspond to the conductive layers respectively.

Ferroelectric memory device and method of forming the same

A semiconductor device includes a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a first lateral direction. The semiconductor device includes third conductive structures each extending along the first lateral direction. The third conductive structures are disposed across the first and second conductive structures. The semiconductor device includes a first semiconductor channel extending along the vertical direction. The first semiconductor channel is disposed between the third conductive structures and the first conductive structure, and between the third conductive structures and the second conductive structure. The first and second conductive structures each have a first varying width along the first lateral direction, and the first semiconductor channel has a second varying width along a second lateral direction.

Semiconductor memory devices with varying channel width and methods of manufacturing thereof

Embodiments of the present disclosure includes a semiconductor device. The semiconductor device includes first suspended nanostructures vertically stacked over one another and disposed on a substrate, a first gate stack engaging the first suspended nanostructures, a first gate spacer disposed on sidewalls of the first gate stack, second suspended nanostructures vertically stacked over one another and disposed on the substrate, a second gate stack engaging the second suspended nanostructures, and a second gate spacer disposed on sidewalls of the second gate stack. A middle portion of the first suspended nanostructures has a first thickness measured in a direction perpendicular to a top surface of the substrate. A middle portion of the second suspended nanostructures has a second thickness measured in the direction. The second thickness is smaller than the first thickness.

Gate all around transistor device and fabrication methods thereof

A method includes forming a plurality of first semiconductor layers and a plurality of second semiconductor layers in an alternate manner over a substrate; patterning the first and second semiconductor layers and the substrate to form a fin structure, in which the fin structure includes a base portion protruding from the substrate and remaining portions of the first and second semiconductor layers; etching the fin structure to form a first recess extending through the remaining portions of the first and second semiconductor layers and into the base portion; epitaxially growing a first epitaxy layer in the first recess; epitaxially growing a second epitaxy layer over the first epitaxy layer; oxidizing the first epitaxy layer, wherein the second epitaxy layer remains unoxidized after the first epitaxy layer is oxidized; and after oxidizing the first epitaxy layer, forming a source/drain epitaxy structure on the second epitaxy layer.

Semiconductor device and manufacturing method thereof

The present disclosure provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes channel members vertically stacked above a substrate, a gate structure engaging the channel members, a gate sidewall spacer disposed on a sidewall of the gate structure, an epitaxial feature abutting end portions of the channel members, and inner spacers interposing the gate structure and the epitaxial feature. The end portion of at least one of the channel members includes a first dopant. A concentration of the first dopant in the end portion of the at least one of the channel members is higher than in a center portion of the at least one of the channel members. The concentration of the first dopant in the end portion of the at least one of the channel members is higher than in an outer portion of the epitaxial feature.

Multi-gate devices and fabricating the same with etch rate modulation

A semiconductor memory device includes a stack of alternating insulating layers and first conductive layers disposed over a substrate; a plurality of memory cell strings penetrating the stack over the substrate, each memory cell string comprising a central portion extending through the stack, a semiconductor layer surrounding the central portion, and a ferroelectric layer surrounding the semiconductor layer, and the central portion comprising a channel isolation structure and a second conductive layer and a third conductive layer at two sides of the channel isolation structure; and a plurality of cell isolation structures penetrating the conductive layers and the insulating layers over the substrate and disposed between two memory cell strings, each cell isolation structure comprising a top portion and a bottom portion adjoined to the top portion and different from the top portion.

Semiconductor memory device and manufacturing method thereof

Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary device includes a channel layer, a first source/drain feature, a second source/drain feature, and a metal gate. The channel layer has a first horizontal segment, a second horizontal segment, and a vertical segment connects the first horizontal segment and the second horizontal segment. The first horizontal segment and the second horizontal segment extend along a first direction, and the vertical segment extends along a second direction. The vertical segment has a width along the first direction and a thickness along the second direction, and the thickness is greater than the width. The channel layer extends between the first source/drain feature and the second source/drain feature along a third direction. The metal gate wraps channel layer. In some embodiments, the first horizontal segment and the second horizontal segment are nanosheets.

Channel configurations with stacked segments for gate-all-around based devices and methods of fabrication thereof

The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.

Integrated circuit structure and method with hybrid orientation for FinFET

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The first nanostructure has a (001) surface, the first nanostructure has a first channel direction on the (001) surface, and the first channel direction is [0 1 0] or [0 −1 0]. The semiconductor device structure includes a gate stack surrounding the first nanostructure. The semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate and over opposite sides of the gate stack. The first nanostructure is between the first source/drain structure and the second source/drain structure, and the first channel direction is from the first source/drain structure to the second source/drain structure.

Semiconductor device structure with channel and method for forming the same

A method includes receiving a semiconductor substrate. The semiconductor substrate has a top surface and includes a semiconductor element. Moreover, the semiconductor substrate has a fin structure formed thereon. The method also includes recessing the fin structure to form source/drain trenches, forming a first dielectric layer over the recessed fin structure in the source/drain trenches, implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer, forming a second dielectric layer over the recessed fin structure in the source/drain trenches, annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure to provide a top surface. Additionally, the method includes forming an epitaxial layer from and on the top surface.

Source/drain features with improved strain properties

The present disclosure provides a method for topography simulation of a physical structure under a topography-changing process. The method includes initializing a voxel mesh as a three-dimensional (3D) representation of the physical structure, generating a batch of particles, simulating a flight path of at least one of the particles with a ray-tracing method, identifying a voxel unit in the voxel mesh that intersects the flight path, determining a surface reaction between the one of the particles and the voxel unit, and adding an extra voxel unit adjacent to the voxel unit based on the determining of the surface reaction.

Semiconductor topography simulation of non-removal type processes

Growing community of inventors

Chubei, Taiwan

Zhiqiang Wu