Globalfoundries Singapore Pte. Ltd.

Zhiqiang Teo

Fan Zhang

Fangxin Deng

Pinghui Li

Laiqiang Luo

Juan Boon Tan

Danny Pak-Chum Shum

Elgin Kiok Boone Quek

Xinshu Cai

Khee Yong Lim

Kin Leong Pey

Soh Yun Siah

Kian Ming Tan

Daxiang Wang

Haiqing Zhou

Pey Kin Leong

Sen Mei

Xingyu Chen

Yu Jin Eugene Kong

Jin Qiu Liu

Lai Qiang Luo

Xin Shu Cai

Eugene Kong

Device and method for forming a device are disclosed. The method includes providing a substrate prepared with a memory cell region having a pair of non-volatile memory cells with a split gate. A split gate includes first and second gates. The first gate is an access gate and the second gate is a storage gate with a control gate over a floating gate. A common second S/D region is disposed adjacent to second gates of the first and second memory cells and first S/D regions are disposed adjacent to the first gates of the first and second memory cells. An erase gate is disposed over the common second S/D region. The erase gate is isolated by the second S/D and second gates by dielectric layers. A silicide block is disposed over the memory cell pair, covering the erase gate at least portions of the second gates of the memory cells.

Reliable non-volatile memory device

A method of forming a uniform WL over the MCEL region and resulting device are provided. Embodiments include providing a substrate having a MCEL region, a HV region and a logic region, separated by an isolation region; forming a plurality of CG stacks over the MCEL region, and a plurality of CG dummy stacks over the HV region and the logic region, respectively; forming first and second overlying polysilicon layers with a spacer therebetween, an EG and a WL on the MCEL region formed; planarizing the second polysilicon layer down to upper surface of the plurality of CG stacks and the plurality of CG dummy stacks; and removing portions of the second polysilicon layer in-between the plurality of CG stacks and around the plurality of CG dummy stacks.

Control gate dummy for word line uniformity and method for producing the same

A method of forming a thick EG polysilicon over the FG and resulting device are provided. Embodiments include forming a CG on a substrate; forming an STI between a logic region and the CG; forming a polysilicon EG through the CG and CG HM; forming a polysilicon structure over the logic and STI; forming and overfilling with polysilicon a WL trench through the CG and CG HM, between the EG and STI; forming a buffer oxide in the polysilicon structure over the logic region and part of the STI; recessing the buffer oxide and etching back the polysilicon overfill down the CG HM; forming a second buffer oxide over the EG and logic region; recessing the WL polysilicon; removing the first and second buffer oxides; forming a mask with an opening over a center of the WL, the STI, and a majority of the logic region; and removing exposed polysilicon.

Method to form thicker erase gate poly superflash NVM

Methods of producing integrated circuits are provided. An exemplary method includes patterning a source line photoresist mask to overlie a source line area of a substrate while exposing a drain line area. The source line area is between a first and second memory cell and the drain line area is between the second and a third memory cell. A source line is formed in the source line area. A source line dielectric is concurrently formed overlying the source line while a drain line dielectric is formed overlying a drain line area. A drain line photoresist mask is patterned to overlie the source line in an active section while exposing the source line in a strap section, and while exposing the drain line area. The drain line dielectric is removed from over the drain line area while a thickness of the source line dielectric in the strap section is reduced.

Method for producing integrated circuit memory cells with less dedicated lithographic steps

Growing community of inventors

Singapore, Singapore

Zhiqiang Teo