Micron Technology Incorporated

Texas Instruments Corporation

Other

Micron Semiconductor, Inc.

Zhiqiang (Jeff) Wu

Li Li

Kunal R Parekh

Alan R Reinberg

Tongbi T Jiang

Paul Hatab

Pai-Hung Pan

Thomas Arthur Figura

Kaiping Liu

Kin F Ma

Pierre C Fazan

Kirk D Prall

Randhir P Thakur

Randhir P S Thakur

Kevin G Donohoe

Craig Thomas Salling

Shaoping Tang

Jihong Chen

Xin Wang

Manny K Ma

Thomas M Graettinger

David Barry Scott

Paul J Schuele

Rongsheng Yang

Che-Jen Hu

Luan C Tran

Shubneesh Batra

Robert B Kerr

Kelly T Hurley

Song Zhao

Salman Akram

Trung Tri Doan

Howard E Rhodes

Theodore Warren Houston

Mark Stephen Rodder

Amitava Chatterjee

Haowen Bu

Philip J Ireland

Seetharaman Sridhar

Amitabh Jain

David Y Kao

Shaofeng Yu

Jau-Yuann Yang

C Rinn Cleavelin

Weize W Xiong

Richard C Hawthorne

Youngmin Kim

Kenneth N Hagen

Ramesh Venugopal

Majid Movahed Mansoorz

Thomas A Figura

Elvia M Hawthorne

A gate stack for an NMOS transistor in an IC to induce tensile stress in the NMOS channel is disclosed. The gate stack includes a first layer of undoped polysilicon, a second layer of n-type polysilicon to establish a desired work function in the gate, layer of compressively stressed metal, and a third layer of polysilicon to provide a silicon surface for subsequent formation of metal silicide. Candidates for the compressively stressed metal are TiN, TaN, W, and Mo. In a CMOS IC, the n-type polysilicon layer and metal layer are patterned in NMOS transistor areas, while the first polysilicon layer and third polysilicon layer are patterned in both NMOS and PMOS transistor areas. Polysilicon CMP may be used to reduce topography between the NMOS and PMOS gate stacks to facilitate gate pattern photolithography.

Method of forming a CMOS IC having a compressively stressed metal layer in the NMOS area

The invention provides a method of fabricating a semiconductor device that enhances the amount of stress that is transmitted to the channel region for carrier mobility enhancement. In one embodiment an amorphous region is formed at or near the gate dielectric interface prior to source/drain anneal. In a second embodiment the gate material is amorphous as deposited and processing temperatures are kept below the gate material crystallization temperature until stress enhancement processing has been completed. The amorphous gate material deforms during high temperature anneal and converts from an amorphous to a polycrystalline phase allowing more stress to be transmitted into the channel region. This enhances carrier mobility and improves transistor drive current.

Method to enhance channel stress in CMOS processes

An integrated process flow for forming an NMOS transistor () and an embedded SiGe (eSiGe) PMOS transistor () using a stress memorization technique (SMT) layer (). The SMT layer () is deposited over both the NMOS transistor () and PMOS transistor (). The portion of SMT layer () over PMOS transistor () is anisotropically etched to form spacers () without etching the portion of SMT layer () over NMOS transistor (). Spacers () are used to align the SiGe recess etch and growth to form SiGe source/drain regions (). The source/drain anneals are performed after etching the SMT layer () such that SMT layer () provides the desired stress to the NMOS transistor () without degrading PMOS transistor ().

Disposable spacer integration with stress memorization technique and silicon-germanium

Multiple blanket implantations of one or more p type dopants into a semiconductor substrate are performed to facilitate isolation between nwell regions subsequently formed in the substrate. The blanket implantations are performed through isolation regions in the substrate so that the p type dopants are implanted to depths sufficient to separate the nwell regions. This increased concentration of p type dopants helps to mitigate leakage between the nwell regions as the nwell regions are brought closer together to increase packing densities.

Method of preparing a semiconductor substrate utilizing plural implants under an isolation region to isolate adjacent wells

A MOS transistor structure comprising a gate dielectric layer (), a gate electrode (), and source and drain regions () are formed in a semiconductor substrate (). First second and third dielectric layers (), (), and () are formed over the MOS transistor structure. The second and third dielectric structures (), () are removed leaving a MOS transistor with a stressed channel region resulting in improved channel mobility characteristics.

CMOS transistor using high stress liner layer

The present invention provides a method () of designing a circuit. The method comprises specifying () a design parameter for memory transistors and logic transistors and selecting () a test retention-mode bias voltage for the memory transistors. The method further comprises determining () a first relationship of a retention-mode leakage current and the design parameter at the test retention-mode bias voltage and obtaining () a second relationship of an active-mode drive current and the design parameter. The first and second relationships are used () to assess whether there is a range of values of the design parameter where the retention-mode leakage current and the active-mode drive current are within a predefined circuit specification. The method also includes adjusting () the test retention-mode bias voltage and repeating the determining and the using if the retention-mode total leakage current or the active-mode drive current is outside of the predefined circuit specification.

Design method and system for optimum performance in integrated circuits that use power management

A semiconductor device is provided with a conductive layer provided on a backside of a semiconductor substrate. The conductive layer helps maintain a uniform bias voltage over the substrate. The conductive layer can also be used to apply a bias voltage to the substrate and reduce the number of bias voltage distribution regions required.

Method and apparatus for reducing substrate bias voltage drop

A technique is disclosed for increasing the width of a transistor () while the transistor itself may be scaled down. The transistor width () is increased by forming recesses () within shallow trench isolation (STI) regions () adjacent to the transistor (). The recesses () provide an area that wraps around the transistor and thereby increases the width () of the transistor (). This wraparound area provides additional space for dopant atom deposition, which facilitates a reduction in random dopant fluctuation (RDF). In this manner, transistors formed in accordance with one or more aspects of the present invention, may yield improved performance when incorporated into SRAM since the probability that such transistors will be more closely matched is increased.

Method to improve SRAM performance and stability

A method of forming a semiconductor device includes implanting a precipitate into a gate conductor of an at least partially formed semiconductor device. The gate conductor including a plurality of semiconductor grains. The boundaries of adjacent grains forming a dopant migration path. A plurality of precipitate regions are formed within the gate conductor. At least some of the precipitate regions located at a junction of at least two grains. The gate conductor of the at least partially formed semiconductor device is doped with a dopant. The dopant diffuses inwardly along the dopant migration path.

Reducing the migration of grain boundaries

The present invention provides a transistorhaving a germanium implant regionlocated therein, a method of manufacture therefor, and an integrated circuit including the aforementioned transistor. The transistor, in one embodiment, includes a polysilicon gate electrodelocated over a semiconductor substrate, wherein a sidewall of the polysilicon gate electrodehas a germanium implanted regionlocated therein. The transistorfurther includes source/drain regionslocated within the semiconductor substrateproximate the polysilicon gate electrode

Method of manufacturing transistor having germanium implant region on the sidewalls of the polysilicon gate electrode

The present invention provides a semiconductor devicehaving a localized halo implantlocated therein, a method of manufacture therefore and an integrated circuit including the semiconductor device. In one embodiment, the semiconductor deviceincludes a gatelocated over a substrate, the substratehaving a source and a drainlocated therein. In the same embodiment, located adjacent each of the source and drainare localized halo implants, each of the localized halo implantshaving a vertical implant regionand an angled implant region. Further, at an intersection of the vertical implant regionand the angled implant regionis an area of peak concentration.

Semiconductor device having a localized halo implant therein and method of manufacture therefor

The present invention provides a semiconductor devicehaving an angled compensation implant, a method of manufacture therefore and a method of manufacturing an integrated circuit including the angled compensation implant. In one embodiment, the method of manufacturing the semiconductor deviceincludes creating a halo implantin a substrate, introducing a compensation implantin the substrateat an angle abnormal to the substrateand forming a source/drain regionabove the compensation implant, the angle reducing a capacitance associated with the halo implantor the source/drain region. The method further includes placing a gate structureover the substrate

Semiconductor device having an angled compensation implant and method of manufacture therefor

Methods are provided for forming wells in a semiconductor wafer, in which p-wells and n-wells are formed in a substrate, and first p-type dopants are implanted into n-well regions while an n-well mask remains over the wafer to selectively decrease a substrate resistivity in the n-well regions beneath the n-wells. A subsequent blanket implantation provides second p-type dopants into isolation regions of the substrate beneath isolation structures, where the first and second p-type dopants improve well to well isolation without addition of extra masks to the fabrication process.

Methods for improving well to well isolation

Growing community of inventors

Meridian, ID, United States of America

Zhiqiang (Jeff) Wu