Shanghai Zhaoxin Semiconductor Co., Ltd.

Via Technologies, Inc.

Via Alliance Semiconductor Co., Ltd.

Zhiqiang Hui

Lin Li

Jingyang Wang

Di Dai

Shanna Pang

Yunxing Dong

Jiin Lai

Wei Shao

Guangyun Wang

Jian Li

Tao Li

Zheng Wang

Xiaoyang Li

Cheng-Wei Huang

Zongpu Qi

Xiaoliang Ji

Chin-Hwaun Wu

Xin-Xi Li

Wanfeng Wang

Shu-Zhi Hou

Jiaping Zhang

Huiying Hou

Hongchao Ma

Lingyan Zhong

A serial transmission controller for processing data transmissions between a memory and an external device is provided. The serial transmission controller includes a microcontroller, a scheduling unit, a transmission unit, and an interception control unit. The microcontroller obtains pipe data from the memory. The microcontroller reads a transfer request block from the memory according to the pipe data. The scheduling unit generates a transmission request according to the pipe data and the transfer request block. The transmission unit transmits a packet of the transfer request block according to the transmission request, and correspondingly generates a transmission response. When the interception control unit receives the transmission response, and the data length that has not been transmitted in the transfer request block is greater than 0, the interception control unit notifies the transmission unit to continue to transmit a next packet of the transfer request block.

Serial transmission controller and data transmission method thereof

A bridging module, a data transmission system, and a data transmission method are provided. The bridging module obtains a first read request, and allocates a first location storage space for first return data corresponding to the first read request. The bridging module combines a first master transaction identifier and an address of the first location storage space as a first slave transaction identifier of the first read request, and sends the first read request to a slave device. The bridging module obtains a second read request, and allocates a second location storage space for second return data corresponding to the second read request. The bridging module combines a second master transaction identifier and an address of the second location storage space as a second slave transaction identifier of the second read request, and sends the second read request to the slave device.

Bridging module, data transmission system, and data transmission method

A bridging module, a data transmission system, and a data transmission method are provided. The bridging module obtains a first read request, and allocates a first data storage space for first return data corresponding to the first read request. The bridging module combines a first master transaction identifier and an address of the first data storage space as a first slave transaction identifier of the first read request, and sends the first read request to a slave device. The bridging module obtains a second read request, and allocates a second data storage space for second return data corresponding to the second read request. The bridging module combines a second master transaction identifier and an address of the second data storage space as a second slave transaction identifier of the second read request, and sends the second read request to the slave device.

A performance analysis system includes a picker module and a calculation circuit. The picker module is placed in the processing device to capture a plurality of pieces of time information of a unit circuit of each of a plurality of tasks in the processing device during total execution time of processing the plurality of tasks. The calculation circuit performs an interval analysis operation on the time information. The interval analysis operation includes: calculating an overlap period between a current task and a previous task; and counting time occupied by the unit circuit during the total execution time of processing the tasks by the processing device according to a relation between the current time interval of the current task corresponding to the unit circuit and the overlap period.

Performance analysis system for analyzing processing performance of processing device and method thereof

A network interface controller including a data alignment module, a boundary determination module and a checksum module is provided. The data alignment module receives raw data and re-combines the raw data as first valid data, wherein the raw data includes a first layer protocol segment and a second layer protocol segment. The boundary determination module receives the raw data in parallel to the data alignment module and performs a boundary determination operation on the raw data to generate a boundary information indicating a boundary between the first layer protocol segment and the second layer protocol segment. The checksum module is coupled to the data alignment module and configured to disassemble the first valid data as second valid data and calculate a checksum according to the boundary information and the second valid data.

Network interface controller

A data compressor with a hash computing hardware configured to evaluate the hash value for the current hash key extracted from a source data string, obtain a hash line corresponding to the hash value from a hash table, and perform hash key comparison to find at least one matching hash key. The hash line includes a prefix address column that stores a prefix address. Each entry of the hash line is provided to store a hash key and an offset. The hash computing hardware evaluates an address of the at least one matching hash key by combining the prefix address and an offset of the at least one matching hash key, and the offset of the at least one matching hash key is obtained from an entry storing the at least one matching hash key.

Data compressor and data compression method

A network interface controller is provided, including a receiving module, a boundary determination module, a first checksum calculation module, and a second checksum calculation module. The receiving module receives a packet having a segment of a first layer protocol and a segment of a second layer protocol. The boundary determination module performs a boundary determination operation on the packet to generate boundary information, wherein the boundary information includes a length of the segment of the second layer protocol and a boundary indication signal. The first checksum calculation module finishes the calculation of a first checksum corresponding to the segment of the first layer protocol after receiving the length of the segment of the second layer protocol. The second checksum calculation module starts to calculate a second checksum corresponding to the segment of the second layer protocol after receiving the boundary indication signal.

A detection control device including a USB connection port, a first detection circuit, a second detection circuit, a control circuit, a first switching circuit and a second switching circuit is provided. When a first pin group of the USB connection port is coupled to an external device, the first detection circuit generates a first detection signal according to a first time constant. When a second pin group of the USB connection port is coupled to the external device, the second detection circuit generates a second detection signal according to a second time constant. The control circuit generates a first control signal and a second control signal according to the first and second detection signals. Each of the first and second switching circuits communicates with the external device via the first or second pin groups according to either the first control signal or the second control signal.

Detection control device

A host controller with suppressed data jitter is shown, which uses a logical physical layer (LPHY) to provide groups of low-speed data, uses a clock-domain-crossing transmitter (TXCDC) to transmit the groups of the low-speed data to the corresponding electrical physical layers (EPHYs), uses the EPHYs to convert the groups of the low-speed data to high-speed data and transmit the high-speed data to the corresponding external devices, and further has a multiplexer. Each EPHY corresponds to one clock signal and operates accordingly. The multiplexer receives the clock signals of the EPHYs to output a common clock signal for the LPHY to provide the groups of low-speed data and for the TXCDC to retrieve the groups of low-speed data. With respect to each of the external devices, the TXCDC uses the clock signal corresponding to the corresponding EPHY to output the corresponding group of low-speed data to the corresponding EPHY.

Host controller of high-speed data interface with clock-domain crossing

A host interface controller having a first buffer set and a second buffer set operated in a ping-pong buffer mode by a control module to alternately work as a pre-fetch buffer set. When one buffer set between the first buffer set and the second buffer set works as the pre-fetch buffer set, the control module pre-fetches and buffers data starting from a first address of a storage device into the pre-fetch buffer set and accesses the other buffer set between the first buffer set and the second buffer set to respond to a read request that the central processing unit issues to access data of a second address of the storage device.

Host interface controller and control method for storage device

A host interface controller with improved boot up efficiency, which uses a buffer mode setting register to set the operation mode of a first and a second buffer set provided within the host interface controller. When a cache memory of a central processing unit (CPU) at the host side has not started up, the first and second buffer sets operate in a cache memory mode to respond to read requests that the CPU repeatedly issues for data of specific addresses of the storage device. When the cache memory has started up, the first buffer set and the second buffer set operate in a ping-pong buffer mode to respond to read requests that the CPU issues for data of sequential addresses of the storage device.

A peripheral interface circuit at host side and an electronic system using the same is disclosed. The peripheral interface circuit has a bus clock signal generator and a data register. The bus clock signal generator outputs a bus clock signal based on a host clock signal to be conveyed to a peripheral device via an interface bus as a reference for the peripheral device to output data. The data register receives the data output from the peripheral device and retrieved at the host side in accordance with the host clock signal. The bus clock signal generator adjusts the bus clock signal based on how the host clock signal is phase-asynchronous to the data output from the peripheral device and retrieved at the host side in accordance with the host clock signal.

Peripheral interface circuit at host side and electronic system using the same

A computer system is provided. In one embodiment, the computer system includes a memory, a peripheral device, a central processing unit (CPU), and a peripheral device controller. The CPU stores information about the data transmission in a descriptor in the memory when data transmission between the CPU and the peripheral device is required. The peripheral device controller reads the descriptor from the memory at an access frequency, records whether the descriptor read from the memory requests for data transmission as a recording result, and adjusts the access frequency according to the recording result.

Method, computer system and control device for reducing power consumption

A USB host controller is provided. The USB host controller is capable of communicating with multiple USB apparatuses having endpoints and sends a request to a first endpoint. The USB host controller includes a first storage and a first control unit. The first control unit stores endpoint information from the first endpoint into the first storage when the first endpoint issues an unready transaction packet in response to the request. The unready transaction packet indicates that the first endpoint is not ready.

Universal serial bus host controller and control method thereof

A USB host control method is provided for a USB host controller. The USB host controller includes a USB device and a buffer, the USB device includes one or more endpoints. The USB host control method includes the steps of: storing first output data to be sent to a first endpoint into one or more buffer units used for the first endpoint; sending the first output data to the first endpoint; and when a first predetermined response from the first endpoint is received, configuring fake releasing labels and information tags corresponding to the first endpoint in the one or more buffer units, and not releasing the one or more buffer units.

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Beijing, China

Zhiqiang Hui