Micron Technology Incorporated

Round Rock Research, LLC

Aptina Imaging Corporation

Zhiping Yin

Gurtej S Sandhu

Weimin Li

Thomas R Glass

Jingyi Bai

Richard D Holscher

Ravi T Iyer

Luan C Tran

John K Lee

D Mark Durcan

Mirzafer K Abatchev

Paul A Morgan

Shuang Meng

William T Rericha

Puneet Sharma

Sheron Honarkhah

Tongbi T Jiang

Xiaofeng Fan

Ramakanth Alapati

Kevin G Duesman

Mark E Jost

Xiangli Li

Steven M McDonald

James E Davis

John B Pusey

Tom Glass

Er-Xuan Ping

Mark Fischer

William Budge

Kunal R Parekh

Fred D Fishburn

Ardavan Niroomand

Gary Chen

Eden M Zielinski

Linda K Somerville

Kevin J Torek

Kevin R Shea

Niraj B Rana

David J Williams

John W Ladd

Mike Connell

Kevin T Hamer

Jeff N Fuss

Raman Alapati

Jingyi (Jenny) Bai

Gurtej Sandhn

Jon Adams

Paul Perez

A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to both the first and second contact pads. The semiconductor device assembly can further include a second die including a third contact pad electrically coupled to a third circuit on the second die including at least a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad and electrically disconnected from the fourth contact pad.

Semiconductor devices with package-level configurability

Pixel array with shared pixels in a single column and associated devices, systems, and methods are disclosed herein. In one embodiment, a pixel array includes a floating diffusion region, a source a source follower transistor having a gate coupled to the floating diffusion region, a plurality of first pixels associated with a first color, and a plurality of second pixels associated with a second color different than the first color and arranged in a single column with the first pixels. The first and second pixels are configured to transfer charge to the floating diffusion region.

Pixel array with shared pixels in a single column and associated devices, systems, and methods

A method and apparatus for reducing space and pixel circuit complexity by using a 4-way shared vertically aligned pixels in a same column. The at least four pixels in the pixel circuit share a reset transistor and a source follower transistor, can have a plurality of same colored pixels and a plurality of colors, but do not include a row select transistor.

Vertical 4-way shared pixel in a single column with internal reset and no row select

An integrated circuit having differently-sized features wherein the smaller features have a pitch multiplied relationship with the larger features, which are of such size as to be formed by conventional lithography.

Integrated circuit having pitch reduced patterns relative to photoithography features

Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.

Pitch reduced patterns relative to photolithography features

An image sensor has an array of pixels of different colors. The pixels may be arranged in a repeating pattern of eight pixels having four rows and two columns. During charge summing operations, the first and third rows may share a floating diffusion and the second and fourth rows may share a floating diffusion. When charge summing is inactive, transfer gates in the first and second columns may be controlled independently, while transfer gates in pairs of rows may be controlled simultaneously. When charge summing is active, summed charges from pixels of the same color in the first and third rows may be placed on the floating diffusion shared by the first and third rows and summed charges from pixels of the same color in the second and fourth rows may be placed on the floating diffusion shared by the second and fourth rows.

Image sensors with pixel charge summing

A photo acid generator (PAG) or an acid is used to reduce resist scumming and footing. Diffusion of acid from photoresist into neighbors causes a decreased acid level, and thus causes resist scumming. An increased acid layer beneath the resist prevents acid diffusion. In one embodiment, the increased acid layer is a layer of spun-on acid or PAG dissolved in aqueous solution. In another embodiment, the increased acid layer is a hard mask material with a PAG or an acid mixed into the material. The high acid content inhibits the diffusion of acid from the photoresist into neighboring layers, and thus substantially reduces photoresist scumming and footing.

Prevention of photoresist scumming

Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern. Pitch multiplication is accomplished by patterning an amorphous carbon layer. Sidewall spacers are then formed on the amorphous carbon sidewalls which are then removed; the sidewall spacers defining the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is transferred to the BARC. The combined pattern is transferred to an underlying amorphous silicon layer. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, is then etched into the underlying substrate.

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Boise, ID, United States of America

Zhiping Yin