Alpha Omega Semiconductor Inc.

Alpha and Omega Semiconductor (cayman) Ltd.

Elantec Semiconductor, Inc.

Zhinan Wei

Allen Chang

Zhiye Zhang

Wai-Keung Peter Cheng

Kevin Ng

A control circuit for a switching regulator implementing a fixed frequency constant on-time control scheme incorporates a reference voltage generator to generate a reference voltage ramp that varies over substantially the entire switching period. In one embodiment, the reference voltage increases from an initial voltage value at the start of each switching period towards the end of the switching period and is reset to the initial voltage value at the end of each switching period. The reference voltage ramp ensures stable feedback control operation in the switching regulator without introducing voltage offset for all output voltage values. The control circuit enables the switching regulator to apply constant on-time control scheme while using an output capacitor having any ESR value, including an output capacitor with low or zero ESR.

Constant on-time switching regulator for zero ESR output capacitor without output voltage offset

A switching regulator controller for a buck switching regulator incorporates a multi-mode adaptive modulator configured to automatically select between a first operation mode and a second operation mode as a function of the output voltage being generated. In one embodiment, the switching regulator controller compares the output voltage to a comparator reference voltage and is configured to operate in a selected operation mode based on the output voltage. In this manner, a single switching regulator controller can be used in multiple instances of an electronic system to supply circuitry that may have different operational requirements. In one embodiment, the switching regulator controller is configured to operation in a PWM/PFM mode and a PWM mode as a function of the output voltage, which indicates the circuit application to which the switch regulator controller is used to supply.

Switching regulator with adaptive PWM/PFM modulator

A current limiting load switch for bridging supply Vss and load with a reference voltage VRdynamically generated by a VR-generator is proposed. It includes: A pair of power FET and sense FET interconnected in split-current configuration. The FET pair develops a load voltage while limiting load current Iload to a preset maximum Imax. The FET pair is sized to draw device currents Ipower and Is with RATIO=Is/Ipower&#x3c;&#x3c;1. The sense FET high-side terminal is coupled to Vss through a sense resistor Rsense developing a sense voltage Vs=Is&#xd7;Rsense. A current limiting amplifier with inputs connected to VRand Vs and output controlling FET pair closing a current limiting feedback loop. The VR-generator dynamically adjusts VRconcurrent and compensatory with an undesirable effect of changing RATIOcaused by the sense FET operational transition thus eliminating a transitional overshoot of Iload beyond Imax.

Current limiting load switch with dynamically generated tracking reference voltage

A circuit and method for controlling a MOSFET based switch that includes two back-to-back FET to block current flow in the OFF state irrespective of the polarity of the voltage differential across the switch. The MOSFET based switch further has a built-in current limit function by sensing the current flow through one of the two MOSFET switches. Furthermore, the bilateral current-limited switch further includes circuitry required for controlling both P type and N type FET in either common drain or common source configuration.

Current limited bilateral MOSFET switch with reduced switch resistance and lower manufacturing cost

A method and apparatus for generating reference voltages for a flat panel display system includes using a digital to analog converter (DAC) to supply multiple reference voltages to the flat panel display system, and wherein the DAC is adapted to accept digital input voltage reference from one of a plurality of registers and is adapted to provide an analog output to a demultiplexer, which includes a plurality of selectable sample and hold circuits.

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San Jose, CA, United States of America

Zhinan Wei