Toshiba Memory Corporation

Koninklijke Philips Corporation N.V.

Nxp B.v.

Greenliant LLC

Anitoa Systems, LLC

Kioxia Corporation

Zhimin Ding

Ata Khan

Gregory Goodhue

Dishi Lai

Naoyuki Kai

Craig A MacKenna

Sancar Kunt Olcay

Pankaj Shrivastava

Li Liu

Fang Wu

Sancar K Olcay

A data storage device comprises a non-volatile semiconductor memory device and a solid-state drive controller communicatively coupled to the non-volatile semiconductor memory device, including a function level reset manager. The function level reset manager can receive a function level reset request from a host system, generate a function level reset bitmap based on the function level reset request, and broadcast the function level reset request to a command processing pipeline. The function level reset bitmap can indicate which functions are in a reset state. Further, the function level reset manager can determine which functions are in the reset state and instruct the command processing pipeline to cancel commands associated with the functions in the reset state.

Managing function level reset in an IO virtualization-enabled storage device

A technique for sharing resources in a data storage device. The data storage device receives a command associated with a non-volatile semiconductor memory device from a host system, the command including a virtual function identifier and a transaction identifier. The data storage device identifies, via a virtual function mapping unit that is included within a controller and that maintains a function mapping table which stores programmable values that associate virtual functions with portions of shared resources of the controller, a portion of a shared resource of the controller based on the virtual function identifier and the transaction identifier. The data storage device accesses the identified portion of the shared resource based on the received command.

Apparatus and method of managing shared resources in achieving IO virtualization in a storage device

Described herein is a chip-based apparatus for amplifying nucleic acids, a cartridge housing the apparatus, and methods of using the apparatus for amplification of nucleic acids. More specifically, this invention provides integrated semiconductor chip, manufactured with standard semiconductor manufacturing process, with on-chip circuitry to perform thermal management and optical sensing necessary for amplification of nucleic acids. The apparatus and methods embodied in this invention makes it possible to build a disease diagnosis and prognosis tool that is easy to use, portable and disposable.

Apparatus for amplification of nucleic acids

Aspects of the disclosure are directed to a system having a particularly-configured microcontroller. In one embodiment, the microcontroller includes the following: a processor; a processor data bus connected to the processor; a set of peripherals; a peripheral data bus connected to the peripherals; a peripheral bus bridge providing an interface between the processor data bus and the peripheral data base and including a plurality of special function register bank blocks that are internal to the microcontroller, each register bank block having a respective output; and a register bank block decoder circuit for decoding interrupts to provide a selection output for activation of one of the plurality of register bank blocks.

Microcontroller with an interrupt structure having programmable priority levels with each priority level associated with a different register set

A secure removable card has electrical connections for communication therewith. The card comprises a first integrated circuit die, with the first die including a processor. The card has a second integrated circuit die, with the second die including a non-volatile memory for storing a secret key, and a controller for controlling the operation of the non-volatile memory. A bus connects the first die with the second die. The processor can generate a key pair, having a public key portion and a private key portion upon power up, and transfers the public key portion across the bus to the second die. The controller can receive the public key and encrypt the secret key with the public key to generate a first encrypted key, and can transfer the first encrypted key across the bus to the first die. The processor can receive the first encrypted key and can decrypt the first encrypted key to recover the secret key, and can encrypt data with the secret key for communicating along the electrical connections external to the card.

Secure removable card having a plurality of integrated circuit dies

All pointer-based accesses require first that the value contained in a pointer register to be read and then that value be used as an address to the appropriate region in random access memory (RAM). As implemented today, this requires two memory read access cycles, each of which takes at least one clock cycle and therefore this implementation does not allow single cycle operation. In accordance with an embodiment of the invention, when an access is performed to pointer memory to read the contents of a pointer, it is the shadow memory that is actually read and that returns the pointer value. Since the shadow memory is made up of pointer registers, a read access involves multiplexing out of appropriate data for the pointer address from these pointer registers to form a target pointer address. This target pointer address is then used as an address to access RAM without the overhead of a clock, since the register access is purely combinatorial and does not require clock-phase related timing as does access to the RAM.

Memory organization allowing single cycle pointer addressing where the address of the pointer is also contained in one of the memory locations

A processing system supports memory access based on distinct memory space access instructions as well as universal access instructions that are independent of memory space partitions. Conventional memory-space dependent instructions, such as MOV, MOVX, and MOVC, provide an optimized addressing scheme, and an extended memory-space independent instruction EMOV provides an optimized code efficiency, processing speed, and ease of code generation. A mapping between the discrete memory space partitions and a &ldquo;universal&rdquo; memory space allocation is provided. The processing hardware interprets the universal address to determine the corresponding memory space, and provides the access to an address within that memory space.

Universal pointer implementation scheme for uniformly addressing distinct memory spaces in a processor's address space

A processing system with extended addressing capabilities includes a control bit that controls the number of address bytes that are stored onto a program stack. If the control bit is set to a first state, the address is pushed onto the program stack in the same manner as that used for shorter-address legacy devices. If the control bit is set to a second state, the address is pushed onto the program stack using the number of bytes required to contain a longer extended address. This same control bit controls the number of bytes that are popped off the stack upon return from an interrupt subroutine. The state of the control bit is controlled by one or more program instructions, thereby allowing it to assume each state dynamically. This dynamic control of the number of bytes pushed and popped to and from the stack allows for an optimization of stack utilization, and thereby further compatibility with legacy devices and applications.

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Sunnyvale, CA, United States of America

Zhimin Ding