Apple Inc.

Zhimin Chen

Timothy R Paaske

Yannick L Sierra

Thomas Icart

Gilbert H Herbeck

Navid Ehsan

Ping Zhou

Nikolai Schlegel

Gerard D Jennings

Jerrold Von Hauck

Andrew Roger Whalley

Conrad Sauerwald

Liran Fishel

Thomas P Mensch

Anish C Trivedi

A processor can include various processing pipelines that perform different data processing operations, with different pipelines having dedicated logic and memory circuits. A power management circuit can determine when to supply power to various pipelines, including the logic and memory circuits of the various pipelines, depending on a current operating mode of the processor. When a memory circuit transitions to a lower power state such as a sleep state, data can be saved to a different memory circuit that is not transitioning to a lower power state, and when the memory circuit is powered up again, the data can be restored from the different memory circuit.

Adaptive wake-up for power conservation in a processor

Embodiments described herein enable the generation of cryptographic material for ranging operations in a manner that reduces and obfuscates potential correlations between leaked and secret information. One embodiment provides for an apparatus including a ranging module having one or more ranging sensors. The ranging module is coupled to a secure processing system through a hardware interface to receive at least one encrypted ranging session key, the ranging module to decrypt the at least one encrypted ranging session key to generate a ranging session key, generate a sparse ranging input, derive a message session key based on the ranging session key, and derive a derived ranging key via a key derivation cascade applied to the message session key and the sparse ranging input, the derived ranging key to encrypt data transmitted during a ranging session.

Methods and architectures for secure ranging

Embodiments relate to switching a neural processor circuit between non-secure and secure modes. A security controller of the neural processor circuit indicates that a transition from the non-secure mode to the secure mode is to occur. The security controller waits for a neural task manager of the neural processor circuit to clear out any existing non-secure tasks in queues. After the existing non-secure mode tasks are cleared, the security controller switches the neural processor circuit to the secure mode. While in the secure mode, secure tasks are added to one or more queues and executed, and data for processing in the neural processor circuit is received from a secure source. The neural processor circuit may to transition back to the non-secure mode when all secure mode tasks are completed.

Secure mode switching in neural processor circuit

A system and method for detecting replay attacks on secure data are disclosed. A system on a chip (SOC) includes a security processor. Blocks of data corresponding to sensitive information are stored in off-chip memory. The security processor uses an integrity data structure, such as an integrity tree, for the blocks. The intermediate nodes of the integrity tree use nonces which have been generated independent of any value within a corresponding block. By using only the nonces to generate tags in the root at the top layer stored in on-chip memory and the nodes of the intermediate layers stored in off-chip memory, an amount of storage used is reduced for supporting the integrity tree. When the security processor detects events which create access requests for one or more blocks, the security processor uses the integrity tree to verify a replay attack has not occurred and corrupted data.

Systems and methods for detecting replay attacks on security space

A method for verifying program flow during execution of a software program in a computer system is disclosed. Program code of the software program includes multiple program instructions and checkpoint data structures, where a given checkpoint data structure is associated with a given program instruction and is linked to at least one other checkpoint data structure. A fault monitor circuit may receive a particular checkpoint data structure and compare the particular checkpoint data structure to a previously received checkpoint data structure that is associated with another program instruction. Based on results of the comparison, the software fault monitor circuit may signal a program flow error.

Software fault monitoring

Systems and methods are disclosed for generating one or more hardware reference keys (HRK) on a computing device, and for attesting to the validity of the hardware reference keys. An initial hardware reference key can be a silicon attestation key (SIK) generated during manufacture of a computing system, such as a system-on-a-chip. The SIK can comprise an asymmetric key pair based at least in part on an identifier of the processing system type and a unique identifier of the processing system. The SIK can be signed by the computing system and stored thereon. The SIK can be used to generate further HRKs on the computing device that can attest to the processing system type of the computing device and an operating system version that was running when the HRK was generated. The computing device can generate an HRK attestation (HRKA) for each HRK generated on the computing system.

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San Jose, CA, United States of America

Zhimin Chen