Texas Instruments Corporation

Zhiliang Julian Chen

Eugene G Dierschke

Hisashi Shichijo

Chin-Yu Tsai

John Gregory Harris

Katsuo Komatsuzaki

Kuok Y Ling

Anli Liu

Thomas A Vrotsos

Steve Clynes

Steven Derek Clynes

Qiang Luo

Xiaochuan Guo

Michael Erwin

Ravi Kishore Kummaraguntla

E Ajith Amerasekera

Ajith E Amerasekera

Steven Derrick Clynes

Zhengwei Zhang

A time domain sampling technique for a CMOS imager enables a wide dynamic range and flexibility by employing up to two-degrees of freedom during such sampling. Two degrees of freedom can be achieved by making one or both of an integration time and a reference (e.g., voltage or current) variable during sampling. The sampling (or image capture) is implemented by associating a time with when a pixel has a desired value relative to the reference in response to the pixel receiving incident light. The reference can be fixed or variable during different portions of the sampling, and further can be programmable to implement a desired sampling pattern for a given application.

System and method to facilitate time domain sampling for solid state imager

Defective pixels in a CMOS array give rise to spot noise that diminishes the integrity of the resulting image. Because CMOS arrays and digital logic can be fabricated on the same integrated circuit using the same processing technology and relatively inexpensive and fast circuit can be employed to digitally filter the pixel data stream and to identify pixels having values that do not fall in the range defined by the immediately neighboring pixels and the deviate from the neighboring pixels by more than a threshold amount. Such conditions would indicate that the deviation is caused by a defective pixel rather than by desired image data. The threshold amount can be preprogrammed or can be provided by a user or can be dynamically set using feedback indicating image quality. The filter would also provide a solution for other sensors such as CCD, although a single chip solution would likely not be possible.

Defective pixel filtering for digital imagers

An imaging architecture is provided employing CMOS imaging sensors. The imaging architecture utilizes time domain sampling techniques to extract image data from a photodiode (PD) pixel array. The CMOS imaging architecture associates time index values with firing of CMOS imaging sensors in response to a capture of an image. The time index values correspond to the brightness of the illumination received by the CMOS imaging sensor. The time index value associated with the firing of the CMOS imaging sensor can be stored and employed in reconstruction of the image. The imaging architecture includes systems and methods for reading and compressing imaging data extracted from the PD pixel array.

Adaptive relative and absolute address coding CMOS imager technique and system architecture

A single capacitor (C) can be used for both readout and noise reduction in an imaging sensor. This dual-purpose use of the single capacitor is facilitated by a switching arrangement (&#x3a6;) which connects the capacitor to a low impedance node (n, n) during charge storage. The low impedance node is also used to drive a column readout line (V).

Stray-insensitive, leakage-independent image sensing with reduced sensitivity to device mismatch and parasitic routing capacitance

The invention comprises a system and method for providing electrostatic discharge protection. In one embodiment of the invention, an integrated circuit () comprising at least one input element () is protected by a protective circuit (). The protective circuit () is operable to protect the integrated circuit () from damage due to electrostatic discharge and may be coupled to the input element (). The protective circuit () comprises a lateral NPN transistor (T) coupled to the input element () and operable to activate when the input element voltage exceeds threshold, the threshold greater than or equal to the ordinary operating voltage of circuitry coupled to the input element (). The protective circuit () also may comprise a lateral PNP transistor (T) coupled to the input element () and to the lateral NPN transistor (T). The lateral PNP transistor (T) is operable to aid in raising a potential of the base of the lateral NPN transistor (T). Alternatively, the protective circuit () also may use a PMOS transistor (P), or a PMOS transistor (P) in combination with the lateral NPN transistor (T), coupled to the input element () and to the lateral NPN transistor (T). The PMOS transistor (P) is operable to aid in raising the potential of the base of the lateral NPN transistor (T).

System and method for electrostatic discharge protection using lateral PNP or PMOS or both for substrate biasing

A digital radio receiver system uses a dual mode automatic gain control architecture and method to enhance signal-to-noise ratio and linearity to accommodate reception and processing of both L-band RF signals and band-III RF signals. The system architecture employs an analog AGC to control high/low gain switches associated with front end low noise amplifiers and down converters, as well as a digital AGC to control gain controlled amplifier and programmable gain amplifier gain settings. The AGC control can be implemented totally within the system architecture or optionally can be implemented via an external data processing device such as a DSP or micro-controller.

System and method of dual mode automatic gain control for a digital radio receiver

Image enhancement is automatically achieved by calibrating the reference voltage and gain of a differential amplifier and the integration interval so as to provide an input to a differential analog to digital converter (ADC) that utilizes the full dynamic range of the ADC. When used with a CMOS array, the imaging logic can be fabricated on a single chip with the array using combinational logic for fast, inexpensive calibration. Another advantageous feature is the ability to expand a desired portion of the luminance spectrum of the image in order to increase the digital resolution of the resulting image for that portion of the spectrum of interest.

Digital imaging control with selective intensity resolution enhancement

The pixels of an image sensor array can be readout ( ) in m&times;n blocks (m, n) that are compatible with the operation of a desired image compression algorithm ( ), thereby reducing the amount of memory required by the image compression algorithm.

Image sensor array readout for simplified image compression

A method for the fabrication of a light-sensing diode in a high-resistivity semiconductor substrate. A high-energy implant of ions into the substrate is patterned to form an annular well of the same conductivity type as the substrate; followed by a second high-energy implant of the opposite conductivity type, within the center of the annulus; followed by a third implant, of lower energy and high dosage, to form a region of the first conductivity type extending laterally near the substrate surface. The resulting diode junction is thereby patterned to include two planes near the substrate surface, allowing incident light to traverse the junction twice.

CMOS photodiode having reduced dark current and improved light sensitivity and responsivity

A MOS architecture for reading rows of pixels in an area array imager. After initial setup, individual pixels are read one row at a time using one clock pulse per pixel.

Fast frame readout architecture for array sensors with integrated correlated double sampling system

This CMOS imager represents illuminance in the time domain. Once per frame, each pixel outputs a pulse after a time proportional to the illuminance on that pixel. Therefore, the illuminance on that pixel is related to the time difference between its pulse event and global reset of the imager. A counter reports the times of these pulse events in a digital format. Thus no analog to digital converter is necessary. This imager enables easy computation of pixel intensity histograms. Frame data is stored in pixel intensity order using row and column arbiters to produce a pixel address. Because each pixel has its own exposure time, the imager has a wide dynamic range of 120 dB. This imager has low power dissipation and avoids the noise and mismatch problems of prior complicated analog readout circuits.

CMOS imager having asynchronous pixel readout in order of pixel illumination

A photodiode sensor ( ) has a photodiode ( ) with an associated capacitance ( ), which may be a parasitic capacitance of the photodiode ( ). A switch ( ) is provided for charging the capacitance ( ) to a predetermined reset voltage (V ), such that when light impinges upon the photodiode ( ), the voltage on the capacitance ( ) discharges in a time proportional to an intensity of the light. A circuit ( ) is also provided for measuring the time for the capacitance ( ) to discharge to a predetermined threshold value ( ), which may be a function of time. The voltage on the output ( ) of the comparator ( ) may be sampled, with the sampling period also being variable as a function of time. The image may be reconstructed from time data indicating the relative times that discharge voltage of the pixels in an array cross the reference voltage ( ).

Time domain sensing technique and system architecture for image sensor

The invention comprises a system and method for providing electrostatic discharge protection. In one embodiment of the invention, an integrated circuit ( ) comprising at least one input element ( ) is protected by a protective circuit ( ). The protective circuit ( ) is operable to protect the integrated circuit ( ) from damage due to electrostatic discharge and may be coupled to the input element ( ). The protective circuit ( ) comprises a lateral NPN transistor (T ) coupled to the input element ( ) and operable to activate when the input element voltage exceeds threshold, the threshold greater than or equal to the ordinary operating voltage of circuitry coupled to the input element ( ). The protective circuit ( ) also may comprise a lateral PNP transistor (T ) coupled to the input element ( ) and to the lateral NPN transistor (T ). The lateral PNP transistor (T ) is operable to aid in raising a potential of the base of the lateral NPN transistor (T ). Alternatively, the protective circuit ( ) also may use a PMOS traisistor (P ), or a PMOS transistor (P ) in combination with the lateral NPN transistor (T ), coupled to the input element ( ) and to the lateral NPN transistor (T ). The PMOS transistor (P ) is operable to aid in raising the potential of the base of the lateral NPN transistor (T ).

A light-sensing diode having improved efficiency due to an extended junction geometry that provides more than one level of interaction with the light input.

Two methods for suppressing the fixed pattern noise effects of a pixel reset switch by ensuring that the reset NMOS device operates in its linear region. The first approach uses a separate reset switch supply voltage, V , set to at least one threshold voltage below the sensing switch supply voltage, V . The second approach uses a charge pump and level shifter to push the reset gate voltage at least one threshold voltage higher than a supply voltage common to both the reset and sense transistors.

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Plano, TX, United States of America

Zhiliang Julian Chen