Tsinghua University

Zhikang Chen

Yu Wang

Yong Feng

Shuxin Liu

The present disclosure relates to the technical field of programmable data planes, and more particularly, to a reconfigurable processor-based programmable switching fabric and a programmable data plane chip. The fabric includes a first side pathway configured to transmit a Packet Header Vector (PHV); a second side pathway configured to transmit data other than the PHV and a control signal; and a reconfigurable processor sequence comprising a plurality of reconfigurable processors in communication with each other via the first side pathway and the second side pathway. Each reconfigurable processor is reconfigurable as a pipeline stage or a Run-to-Complete (RTC) processor. A data pathway for transmitting the PHV is provided each pair of adjacent reconfigurable processors. Different connection operations are performed based on the reconfigurable processors at two ends of the data pathway.

Reconfigurable processor-based programmable switching fabric and programmable data plane chip

A method and an apparatus for updating a programmable data plane at runtime are provided. The method includes: splitting, based on distributed on-demand parsers of the data plane, a parsing graph into parsing sub-graphs, and distributing each parsing sub-graph to a respective physical stage in a virtual pipeline of the data plane; adjusting, based on template-based processors and the virtual pipeline, an order between any two template-based processors by configuring an interconnection network; disaggregating and pooling, based on a decoupled resource pool of the data plane, flow table resources of each physical stage, and updating a flow table at runtime; and suspending, based on a fast update controller of the data plane, packet processing prior to a to-be-updated template-based processor, and configuring or deleting the template-based processor from the pipeline when the template-based processor has no packet.

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Beijing, China

Zhikang Chen