Shenzhen Microbt Electronics Technology Co., Ltd.

Zhijun Fan

Zuoxing Yang

Haifeng Guo

Chao Xu

Wenbo Tian

Nan Li

Weixin Kong

Ke Xue

Dong Hai Yu

Danyang Wang

Yun Zhai

Jianbo Liu

Lianhua Duan

Chuan Gong

Mo Chen

Tianzhi Xue

Shuangyan Chen

A test circuit (), including: a test sequence providing module (), configured to provide a test sequence (PRBS) to a to-be-tested sequential device (); a clock driving module (), configured to provide a clock signal () to the to-be-tested sequential device (), which includes a first clock driving circuit (), wherein the first clock driving circuit () includes: a plurality of first clock paths () which respectively provide corresponding clock signals (); and a logic unit () which generates, based on at least part of the clock signals () provided by the plurality of first clock paths (), a first clock signal with an adjusted pulse width, for the to-be-tested sequential device (); and a verification module (), configured to verify an output of the to-be-tested sequential device ().

Test circuit, test method, and computing system comprising test circuit for testing sequential circuit in pipeline stage

The present disclosure relates to a multiplier, a multiply-accumulate circuit, an operational circuit, a processor, and a calculation apparatus. The operational circuit includes an input processing circuit and the multiply-accumulate circuit. The input processing circuit receives a first number and outputs the first number as a first multiplicator for feeding into the multiply accumulate circuit by negating a sign bit of the first number in a case in which the first number is a signed number, and directly outputs the first number as the first multiplicator for feeding into the multiply-accumulate circuit in a case in which the first number is an unsigned number. The input processing circuit further receives a previously known second number and directly outputs the second number as a second multiplicator for feeding into the multiply-accumulate circuit. The multiply-accumulate circuit includes a multiplication subcircuit and an accumulation subcircuit.

Multiplier, multiply-accumulate circuit, operational circuit, processor, and calculation apparatus

The present disclosure relates to a multiplier, a multiply-accumulate circuit, and a convolution operation unit. The multiplier includes: one or more selection circuits, each of the one or more selection circuits respectively configured to select a target preset multiple of a first operand from a preset multiple of a first operand as a fourth operand according to a corresponding third operand, wherein the target preset multiple is equal to a value of the third operand; and a partial product summing circuit, each of one or more input terminals of the partial product summing circuit respectively connected to an output terminal of corresponding one of at least one or more selection circuits, wherein the partial product summing circuit is configured to calculate a partial product sum of one or more fourth operands from the one or more selection circuits.

Multiplier, multiply-accumulate circuit, and convolution operation unit

The present disclosure relates to a D flip-flop having a multiplexer function, including: a first transmission gate whose data input end is configured to receive a first data signal and whose clock input end is configured to receive a first clock signal; a second transmission gate whose data input end is configured to receive a second data signal and whose clock input end is configured to receive a second clock signal; an inverted latch unit whose data input end is connected to an output end of the first transmission gate and an output end of the second transmission gate and whose clock input end is configured to receive a third clock signal; and an inverter whose input end is connected to an output end of the inverted latch unit and whose output end provides an output of the D flip-flop.

D flip-flop having multiplexer function

This disclosure relates to a divider, a processor, and a calculation apparatus. The divider includes: a first-stage shift circuit, configured to shift a received first operand to left to generate a second operand; a first-stage selection circuit, configured to select a first preset multiple of a third operand as a fourth operand from preset multiples of the third operand; and a first-stage operational circuit, configured to calculate an OR operation result of the first preset multiple and a difference between the second operand and the fourth operand as a fifth operand.

Divider, processor, and calculation apparatus

A dynamic D flip-flop with an inverted output involves an input end () used for receiving input data; an output end () used for providing output data to respond to the input data; a clock signal end () used for receiving a clock signal; a first latch () used for latching the input data from the input end () and performing inverting transmission on the input data under the control of the clock signal; a second latch () used for latching data from the first latch () and performing inverting transmission on the data latched by the first latch () under the control of the clock signal; and an inverter () used for performing inverting output on the data received from the second latch (), the first latch (), the second latch (), and the inverter () being sequentially connected in series between the input end and the output end.

Dynamic D flip-flop with an inverted output

The present disclosure relates to clock circuits, computing chips, hash boards and data processing devices. A clock circuit comprises M stages of clock drive circuits that are connected in series, M being an integer that is no less than 2, wherein N inverters connected in series are arranged between an input port and an output port of each stage of the M stages of clock drive circuits, N being an odd number that is no less than 3. The clock circuit may provide clock signals with excellent performance.

Clock circuits, computing chips, hash boards and data processing devices

A D flip-flop, a processor including the D flip-flop, and a computing apparatus. A D flip-flop is provided, including: an input stage configured to receive a flip-flop input; an output stage configured to output a flip-flop output; an intermediate node disposed between an output of the input stage and an input of the output stage, where the output stage is configured to receive a signal at the intermediate node as an input; an intermediate stage configured to receive the output of the input stage and provide the output to the intermediate node; and a feedback stage configured to receive the flip-flop output and provide a feedback to the intermediate node, where the feedback stage assumes a logic-high state, a logic-low state, and a high-impedance state.

D flip-flop, processor including the d flip-flop, and computing apparatus

The present disclosure relates to a latch, a processor including the latch, and a computing apparatus. A latch with an inverted output is provided, including: an input stage configured to receive a latch input; an output stage configured to output a latch output; an intermediate node disposed between an output of the input stage and an input of the output stage, wherein the output stage is configured to receive a signal at the intermediate node as an input; and a feedback stage configured to receive the latch output and provide a feedback to the intermediate node, wherein feedback stage assumes a logic-high state, a logic-low state, and a high-impedance state, wherein the latch output is inverted from the latch input.

Latch, processor including latch, and computing apparatus

This disclosure relates to a pipeline clock driving circuit, a computing chip, a hashboard and a computing device. A pipeline clock driving circuit provides a pulse clock signal to a pipeline comprising multiple operation stages. The pipeline clock driving circuit includes multiple stages of clock driving circuits, each configured to provide the pulse clock signal to one corresponding operation stage; and a clock source coupled to an input of a first stage of clock driving circuit and configured to provide a basic clock signal. Inputs of other stages of clock driving circuits are coupled to outputs of previous stages of clock driving circuits. Each stage of clock driving circuit includes: a trigger; a delay module for outputting a delayed pulse signal to a next stage of clock driving circuit; and a combinational logic module for performing a combinational logic operation on the outputs to generate the pulse clock signal.

Pipeline clock driving circuit, computing chip, hashboard and computing device

A computing device and a computing system for digital currency are disclosed. The computing system comprises: computing devices (comprising first and second computing devices) each comprising two ports; and a signal transmission path connecting the computing devices in series. Each computing device is connected to the signal transmission path via the two ports. The first computing device is configured to receive, from the signal transmission path through one of the two ports, a signal specific to an address of the first computing device to a local storage device thereof. The second computing device is configured to receive, from the signal transmission path through one of the two ports, a signal to a local storage device thereof, and forward the signal, which is not specific to an address of the second computing device, or an adjusted version of the signal to the signal transmission path through one of the ports.

Computing device and computing system for digital currency

The present disclosure relates to a pipeline clock driving circuit, a computing chip, a hashboard, and a computing device. Disclosed is a pipeline clock driving circuit, configured to provide a pulse clock signal to a pipeline, including: a plurality of stages of clock driving circuits, each stage being configured to provide the pulse clock signal to a corresponding operation stage of the pipeline; a clock source, coupled to an input of a first-stage clock driving circuit, each stage of the clock driving circuits including: a trigger, coupled to an input of a current-stage clock driving circuit; a delay module, including a first delay sub-module, the first delay sub-module delaying a pulse signal output by the trigger and feeding a delayed pulse signal back to the trigger as a feedback pulse signal; and a combinational logic module, performing a combinational logic operation on the pulse signal and the feedback pulse signal to generate the pulse clock signal to be provided to a corresponding operation stage, where the delay module further includes a second delay sub-module, and the second delay sub-module delays the pulse signal and outputs the delayed pulse signal to a next-stage clock driving circuit.

Pipeline clock driving circuit, computing chip, hashboard, and computing device

The present disclosure relates to a chip placed in a full-custom layout and an electronic device for implementing a mining algorithm. There is provided a chip placed in a full-custom layout, comprising a pipeline structure having a plurality of operation stages, wherein each operation stage includes: a plurality of rows arranged sequentially in an X-direction parallel to a substrate of the chip and having a uniform row height in the X-direction, the plurality of rows including rows of a first type, each row of the first type including: a first set of register modules; and a first set of logical operation modules; wherein the first set of register modules and the first set of logical operation modules are adjacently provided in a Y-direction, and the first set of logical operation modules is used for processing data in the first set of register modules.

Chips placed in full-custom layout and electronic device for implementing mining algorithm

The present disclosure relates to a composite logic gate circuit, including: a simple logic gate circuit including a first logic gate circuit and an inverter circuit, a first PMOS transistor, and a first NMOS transistor. The first logic gate circuit is configured to receive a first input signal and a second input signal, and to output a first output signal. The inverter circuit includes a second PMOS transistor and a second NMOS transistor. A source of the second PMOS transistor is coupled to a power input terminal, a drain is coupled to a drain of the second NMOS transistor, and a gate is configured to receive the first output signal. A source of the second NMOS transistor is coupled to a ground terminal, and a gate is configured to receive the first output signal. A source of the first PMOS transistor is coupled to the drain of the second PMOS transistor, a drain is coupled to a drain of the first NMOS transistor, and a gate is configured to receive a third input signal. A source of the first NMOS transistor is configured to receive the first output signal, and a gate is configured to receive the third input signal. The simple logic gate circuit is an AND or OR gate circuit, and the first logic gate circuit is a NAND or NOR gate circuit.

Composite logic gate circuit

Circuits and methods for performing a hash algorithm are disclosed. A circuit includes: an input module receiving data; and an operation module calculating a hash value based on the received data. The operation module includes multiple operation stages (0th operation stage, 1st operation stage, up to P-th operation stage, P being a fixed positive integer greater than 1 and less than the number of operation stages in a pipeline structure) arranged in the pipeline structure. Each of the 1st operation stage to P-th operation stage includes: cache registers storing intermediate values of a current operation stage and operating at a first frequency, and extension registers storing extension data of the current operation stage and the extension registers comprising a first set of extension registers operating at the first frequency and a second set of extension registers operating at a second frequency which is 1/N times the first frequency.

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Guangdong, China

Zhijun Fan