Freescale Semiconductor,inc.

Nxp USA, Inc.

Zhijun Chen

Zhihong Cheng

Zhiling Sui

SHixiang Nie

Wangsheng Mei

Peidong Wang

Yang Liu

Yan Xiao

Jurgen Geerlings

Liang Jia

Jiangtao Pan

Yanping Zhang

Li Ying

A method for direct memory access includes: receiving a direct memory access request designating addresses in a data block to be accessed in a memory; randomizing an order of the addresses the data block is accessed; and accessing the memory at addresses in the randomized order. A system for direct memory access is disclosed.

System and method for direct memory access

A multi-core processor manages contention amongst its cores for access to a shared resource using a semaphore that maintains separate access-request queues for different cores and uses a selectable scheduling algorithm to grant pending requests, one at a time. The semaphore signals the core whose request is granted by sending it an interrupt signal using a dedicated core line that is not part of the system bus. The granted request is then de-queued, and the core accesses the shared resource in response to receiving the interrupt signal. The use of dedicated core lines for transmitting interrupt signals from the semaphore to the cores alleviates the need for repeated polling of the semaphore on the system bus. The use of the scheduling algorithm prevents a potential race condition between contending cores.

Semaphore for multi-core processor

A frequency shift keying (FSK) demodulation component having of a sampler that receives an FSK modulated signal, samples the received FSK modulated signal, and outputs the sampled signal. The FSK demodulation component further includes a low pass filter that filters the sampled signal, and a frequency shift detector that detects shifts in frequency of the low pass filtered sampled signal. The FSK demodulation component then outputs an indication of the detection of shifts in frequency of the low pass filtered sampled signal.

Wireless charger using frequency aliasing FSK demodulation

A method of demodulating an FSK modulated input signal whose frequency varies between first and second frequencies. The input signal is delayed by a plurality of cycles, providing a second signal. A succession of phase reference signals having respective incrementally greater phase delays relative to the input signal are provided. Samples of the phase reference signals are taken at intervals determined by the second signal. A transition between the first and second frequencies is detected when the relative values of the samples of the phase reference signals remain constant during a plurality of intervals after varying. A high speed clock is not required to perform the demodulation.

Demodulating frequency shift keying modulated input signal

A demodulator suitable for demodulating binary FSK signals having a small difference between carrier frequencies uses a counter-timer technique for timing a fixed number FSK cycles and comparing a count value with a threshold when a frequency change is expected. By grouping a number of FSK pulses (or cycles) together in one measurement, speed requirements on the system clock used for the counter/timer measurements can be relaxed and tolerance to noise is also improved. The demodulator is particularly suitable for wireless charging applications.

FSK demodulator

A pipelined analog-to-digital converter (ADC) that converts an analog input voltage signal Vinto a digital output value D. The ADC has a sequence of stages including a first calibrated stage having: (1) an ADC sub-module that receives Vand provides an ADC sub-module digital output value based on V, (2) a DAC sub-module that receives the ADC sub-module digital output value and outputs a corresponding analog voltage signal V, (3) a first difference module that generates an analog residual-voltage signal based on a difference between Vand V, and (4) an artificial-noise-insertion module that inserts an analog artificial-noise voltage signal into the residual voltage signal to generate an analog combined voltage signal. The analog combined voltage signal is used to calibrate the first calibrated stage. The artificial-noise-insertion module generates the polarity of the artificial-noise voltage signal based on the polarity of the corresponding residual voltage signal.

Analog-to-digital converter with controlled error calibration

A system for optimizing the number of dies that can be fabricated on a wafer uses a die number optimization (DNO) routine to determine a maximum number of dies for a target die area (TDA), and generate an initial result list of die shapes that have the maximum number of dies for the TDA. Optionally, a die size optimization (DSO) routine can be executed to determine a list of die shapes having a maximum die area corresponding to the maximum number of dies, a first list of optimized die shapes having a maximum area utilization (AU) for a decreased TDA, and/or a second list of optimized die shapes having a minimum AU for an increased TDA. A candidate list (CL) of the various die shapes can be generated, and entries from the CL automatically selected and/or displayed to indicate proposed wafer layouts.

System for optimizing number of dies produced on a wafer

A processor with programmable virtual ports includes a plurality of in/out (IO) pins for transmitting and receiving data. The IO pins are grouped into a plurality of predefined ports, each of which has a physical address stored in one of a memory location of a memory map. The IO pins may be remapped to one or more virtual ports.

Processor with programmable virtual ports

A stepper motor controller includes control circuitry with control outputs and individual driver pulse width modulation (PWM) circuitry with individual driver PWM outputs and modulation control inputs coupled to the control outputs. There is a group of individual drivers, each one having an input coupled to one of the PWM outputs, and an output coupled to an individual driver terminal of the controller. There is common driver PWM circuitry having a common driver PWM output. A common driver having a common driver input is coupled to the common driver PWM output and a common driver output is coupled to a common driver terminal of the controller. When a coil is connected between respective driver terminals and the common driver terminal, individual PWM driver currents are supplied to the coils from the individual driver terminals and a common PWM driver current is supplied to the coils from the common driver terminal.

Growing community of inventors

Suzhou, China

Zhijun Chen