Freescale Semiconductor,inc.

Nxp USA, Inc.

Nxp B.v.

Zhijie Wang

You Ge

Zhigang Bai

Meng Kong Lye

Huchang Zhang

Yanbo Xu

Fei Zong

Jinzhong Yao

Dehong Ye

Aipeng Shu

Zhe Li

Jiyong Niu

Kabir J Mirpuri

Nan Xu

Qingchun He

Mariano Layson Ching, Jr

Jinsheng Wang

Jianshe Bi

Weimin Chen

Chao Wang

Yit Meng Lee

Guanhua Wang

Changliang Zhang

Yingwei Jiang

Mei Liu

Wei Xiao

Qing Chun He

Zhimei Sun

Wei Chen

A Quad Flat No-Lead (QFN) package comprises a semiconductor die, a lead frame and molding compound. The lead frame comprises a die pad having a substantially rectangular inner part and a plurality of protrusions around the periphery thereof and contiguous therewith and extending outwardly therefrom, and a plurality of leads around the four sides of the die-pad. The molding compound encapsulates the semiconductor die and forming the package. The molding compound has a respective moat therein between each side of the die pad and a respective set of leads. The die pad has a plurality of trenches extending from the second surface of the die pad towards the first surface at least in the inner part of the die pad. The plurality of the trenches each extend across a protrusion to the moat.

QFN semiconductor package, semiconductor package and lead frame

A semiconductor package comprises a lead frame, a die pad, bond pads, and leads. A die may be arranged on the die pad, the die comprising an integrated circuit. In an example, the die and at least a portion of the lead frame are encapsulated with a molding compound (MC). A first thickness of the MC over a first portion of the die is less than a second thickness over a second portion of the die to form a cavity in the MC and the MC directly contacts the first portion and the second portion of the die.

Cavity formed in a molding compound of a semiconductor package to reduce mechanical stress on a portion of a die in the package, and methods of formation

A power die package includes a lead frame having a flag with power leads on one lateral side and signal leads on one or more other lateral sides. A power die is attached to a bottom surface of the flag and electrically connected to the power leads with a conductive epoxy. A control die is attached to a top surface of the flag and electrically connected to the signal leads with bond wires. A mold compound is provided that encapsulates the dies, the bond wires, and proximal parts of the leads, while distal ends of the leads are exposed, forming a PQFN package.

Power die package

A flexible semiconductor device includes a first tape having bonding pads and conductive traces formed. A semiconductor die having a bottom surface is attached to the first tape and electrically connected to the bond pads by way of electrical contacts. A second tape is attached to a top surface of the semiconductor die. The first and second tapes encapsulate the semiconductor die, the electrical contacts, and at least a part of the conductive traces.

Method of making flexible semiconductor device with graphene tape

A semiconductor device is assembled using a lead frame having leads that surround a central opening. The leads have proximal ends near to the central opening and distal ends spaced from the central opening. A heat sink is attached to a bottom surface of the leads and a semiconductor die is attached to a top surface of the leads, where the die is supported on the proximal ends of the leads and spans the central opening. Bond wires electrically connect electrodes on an active surface of the die and the leads. An encapsulant covers the bond wires and at least the top surface of the leads and the die. The distal ends of the leads are exposed to allow external electrical communication with the die.

Semiconductor device with lead frame that accommodates various die sizes

Flexible semiconductor device with graphene tape

A method of assembling QFP devices includes providing a lead frame having leads that extend from a dam bar to a die flag, and performing a first molding process that fills spaces between the leads and between the dam bar and the die flag with a first mold compound. The first mold compound also forms a ring around the die flag, where the ring extends from both lateral sides of the lead frame. A first area around the die flag is removed to separate the leads from the die flag, and a second area near an inner corner of the dam bar is removed to form a mold gate. A die is attached to the die flag and electrically connected to the leads with bond wires, and then a second molding process is performed to encapsulate the die, bond wires and inner leads.

Method of assembling QFP type semiconductor device

A semiconductor device includes a lead frame having leads arranged in an array that has columns extending in a first direction and rows extending in a second direction. Each lead includes a bond pad portion and a solder pad portion down-set from the bond pad portion. The solder pad portion horizontally extends from the bond pad portion in the first direction. A semiconductor die is mounted on a set of the plurality of leads and electrically connected to the bond pad portion of at least one of the plurality of leads. The semiconductor die, and the plurality of leads are encapsulated by a molding material, wherein the molding material defines a package body, and the solder pad portion of each lead is exposed at a back side of the package body.

Semiconductor device and lead frame with high density lead array

A woven signal-routing substrate for a wearable electronic device has conductive warps and wefts that are woven with each other and with insulative warps and wefts. Woven electrical cross-connections are formed at some of the intersections of the conductive warps and wefts, while no electrical cross-connections are formed at other intersections, to provide a signal-routing architecture for the substrate that can be used to route signals between electronic components of the wearable device. Non-connecting intersections are formed using insulative warps that are sufficiently thicker than the relatively thin conductive warps to enable a conductive weft to cross a conductive warp without making physical contact at intersection locations where an electrical cross-connection is not desired. The woven electrical cross-connections may be formed at other intersection locations using weaving topologies that ensure that the corresponding mutually orthogonal warps and wefts do contact one another.

Woven signal-routing substrate for wearable electronic devices

A semiconductor sensor device is assembled using a lead frame having a flag surrounded by lead fingers. A pressure sensor die is mounted on the flag and electrically connected to the leads. Prior to encapsulation, a pre-formed block of gel material is placed over the sensor region on the die. Encapsulation is performed and mold compound covers the pressure sensor die and the bond wires. Mold compound covering the gel block may be removed. Additionally, a trench may be formed around an upper portion of the gel block so that the lateral sides of the gel block are at least partially exposed.

Cavity type pressure sensor device

A semiconductor package has a lead frame and a power die. The lead frame has a first die paddle with a cavity formed entirely therethrough. The power die, which has a lower surface, is mounted on the first die paddle such that a first portion of the lower surface is attached to the first die paddle using a solderless die-attach adhesive, and a second portion of the lower surface, is not attached to the first die paddle and abuts the cavity formed in the first die paddle such that the second portion is exposed.

Exposed die power semiconductor device

An integrated circuit (IC) package has a base, side walls mechanically connected to the base, IC dies respectively mounted on inner surfaces of the side walls or the base, and electrical connections connecting a corresponding IC die to another component of the IC package. In one embodiment, each die is electrically connected to only bond pads on its corresponding side wall or base. Each such side wall and the base have routing structures (e.g., copper traces) that connect each bond pad to another component of the IC package. The IC package is assembled using a flexible substrate that has side regions that rotate relative to the base such that the routing structures do not break. By connecting an IC die only to bond pads on its corresponding side wall or base with bond wires, the bond wires will not break during side-wall rotation.

IC package having non-horizontal die pad and flexible substrate therefor

A cleaning subsystem removes unwanted material, such as glaze, from saw blades used in a semiconductor singulation process. A cleaning module moves radially towards the saw blade and vertically with respect to the plane of the saw blade in order to enable abrasive cleaning blocks of the cleaning module to selectively remove material from either the upper and lower surfaces of the saw blade or the outer edge of the saw blade. The cleaning assembly can remove material from the saw blade at a predetermined time or position during the singulation process or upon detection of load imbalance during the rotation of the saw blade.

Cleaning mechanism for semiconductor singulation saws

A packaged integrated circuit (IC) device having a heatsink mounted onto an IC die, itself mounted onto a die pad, is assembled using a lead frame having tie bars that deflect during an encapsulation phase of the device assembly, which enables the die pad, the die, and the heatsink to move relative to the lead frame support structure when compressive force is applied by the molding tool. This movement results in negligible relative displacement between the heatsink and the die during encapsulation, which reduces the probability of physical damage to the die. Each tie bar has a number of differently angled sections that enable it to deflect when compressive force is applied to it.

Lead frame with deflecting tie bar for IC package

A semiconductor wafer has a multi-stage structure that damps and contains nascent cracks generated during dicing and inhibits moisture penetration into the active region of a die. The wafer includes an array of die regions separated by scribe lanes. The die regions include an active region and a first ring that surrounds the active region. A portion of the first ring includes a low-k dielectric material. A second ring includes a stack of alternating layers of metal and interlayer dielectric (ILD) material. A dummy metal region around the rings includes a stacked dummy metal features and surrounds the active region. A regular or irregular staggered arrangement of saw grid process control (SGPC) features reduces mechanical stress during dicing.

Growing community of inventors

Tianjin, China

Zhijie Wang