Boe Technology Group Co., Ltd.

Beijing Boe Display Technology Co., Ltd.

Beijing Boe Technology Development Co., Ltd.

Hefei Xinsheng Optoelectronics Technology Co., Ltd.

Chongqing Boe Optoelectronics Technology Co., Ltd.

Hefei Boe Display Technology Co., Ltd.

Beijing Boe Display Technology Technology Co., Ltd

Zhihua Sun

Yanping Liao

Xibin Shao

Yingmeng Miao

Feng Qu

Seungmin Lee

Yinlong Zhang

Shulin Yao

Qiujie Su

Baoyu Liu

Xu Zhang

Guohuo Su

Jiantao Liu

Yingying Qu

Jianming Wang

Weichao Ma

Liang Zhang

Yizhen Xu

Yifu Chen

Jianhua Huang

Wenpeng Ma

Chongyang Zhao

Zhihao Zhang

Xingji Wu

Pengfei Hu

Senwang Li

Lei Guo

Ning Zhang

Ting Dong

Cong Wang

Yujie Gao

Changcheng Liu

Jituo Tang

Haipeng Yang

Honglin Zhang

Junjie Guo

Maoxiu Zhou

Xiaochun Xu

Lingdan Bo

Ming Deng

Wenliang Liu

Jinling Zhang

Jianbo Xian

Jian Li

Qi Cheng Li

Jing Liu

Ke Dai

Zhe Li

Li Tian

Xiaofeng Yin

Feifei Wang

Liangliang Jiang

Zhangtao Wang

Yue Yang

Lifeng Lin

Yuntian Zhang

Lan Xin

Seung Min Lee

Deqiang Liu

Guangquan He

Liangliang Zhao

Zhun Lin

Kaiming Shi

Yinshu Zhang

Yu Zhang

Hui Zhang

Tao Yang

Song Liu

Hebin Zhao

Dongchuan Chen

Li Ni Zhang

Xiaoyuan Wang

Ying Huang

Wenkai Mu

Qi Li

Ning Zhu

Lisheng Liang

Ruilian Li

Xiuqin Zhang

Wenhai Cui

Shuming Wang

Hongli Yue

Wenjie Hou

Yanjiao Pan

Tianxun Xiu

Weihai Li

Tong Lu

Zhiyu Lv

Changchen Liu

Chengri Quan

Xiangyang Zheng

Xueliang Yang

Jing Ma

A temperature control circuit of a driver chip, a temperature control method of the driver chip, a power management integrated chip, a timing control driver board and a display apparatus are disclosed. The temperature control circuit includes a switching transistor, a comparison circuit and a control circuit; a first electrode of the switching transistor is connected with a first node, a second comparison end and the first electrode or a second electrode of the switching transistor are connected to a second node; the control circuit is configured to output a first reference voltage to the comparison circuit, the comparison circuit is configured to compare a magnitude relationship between a voltage on the second comparison end and the first reference voltage and output a comparison result; the control circuit acquires the comparison result and determines whether an output current on the boost circuit is excessively large.

Temperature control circuit and temperature control method of driver chip and timing control driver board

There is provided a gate driving circuit, a display panel and a driving method of the gate driving circuit. The gate driving circuit includes multiple stages of shift registers. The multiple stages of shift registers comprise N first shift registers arranged alternately with N second shift registers. The N first shift registers are cascaded-coupled as N stages of first shift registers, and are configured to generate N first output signals under control of K first clock signals. The N second shift registers are cascaded-coupled as N stages of second shift registers, and are configured to generate N second output signals under a control of K second clock signals. K and N are both integers greater than 1, and K≤N.

Gate driving circuit and driving method thereof and display panel

A display panel, comprising open areas; a non-open area; an array substrate comprising a first substrate and gate lines, data lines, thin film transistors and raised portions located in the non-open area, wherein orthographic projections of the data lines on the first substrate have overlaps with orthographic projections of the gate lines on the first substrate, orthographic projections of the raised portions on the first substrate are located within the orthographic projections of the gate lines on the first substrate; and a color filter substrate comprising a second substrate and spacers located on a side of the second substrate; wherein orthographic projections of the spacers on the first substrate have overlaps with the orthographic projections of the raised portions and overlapping parts of the data lines and the gate lines on the first substrate.

Display panel and display device

A display driving method and a display device are provided. The display driving method includes: scanning a plurality of subpixels arranged in an NΔM array row by row or in multiple rows to turn on each row of scanned subpixels, so that the duration when two adjacent rows of subpixels are simultaneously in a turn-on state is greater than or equal to two times a unit scan time, the unit scan time being the time required for scanning one row of subpixels, and N and M both being integers greater than 1; and applying data signals to at least two rows of subpixels that are simultaneously in the turn-on state, so that the duration when data signals are applied to at least some rows of subpixels is greater than the unit scan time.

Display driving method for increasing charging duration and display device

The present disclosure relates to a touch display device and a driving method for the touch display device. The touch display device comprises data lines, gate lines, pixel electrodes located within display areas defined by the data lines and the gate lines, and a driving circuit. The driving circuit is configured to provide a first display data signal to the data lines during a display stage of the touch display device, and is configured to provide a second display data signal to the data lines during a predetermined period adjacent to the display stage within a touch stage of the touch display device, and provide an off-signal to the gate lines during the predetermined period such that the second display data signal is not provided to the pixel electrodes.

Touch display device and driving method for the touch display device

An array substrate and a display device are provided. The array substrate includes a base substrate, a plurality of data lines extending along a first direction and a plurality of gate lines extending along a second direction, and a plurality of pixel units defined by the gate lines and the data lines. The pixel unit includes a thin-film transistor, a common electrode and a pixel electrode. The thin-film transistor includes a gate electrode, a source and drain electrode and an active layer. The pixel unit also includes a first auxiliary electrode and a second auxiliary electrode. The first auxiliary electrode is electrically connected to the common electrode, and the second auxiliary electrode is electrically connected to the source and drain electrode. An orthographic projection of the first auxiliary electrode on the base substrate at least partially overlaps an orthographic projection of the second auxiliary electrode on the base substrate.

Array substrate comprising first and second auxiliary electrodes, and display device

The present disclosure provides an array substrate and a display device. The array substrate includes one start data line, N−1 intermediate data line and one end data line. The array substrate further includes a first driving circuit and a second driving circuit, the first driving circuit is arranged at a first side of the plurality of data lines, and the second driving circuit is arranged at a second side of the plurality of data lines opposite to the first side in a first direction. The first driving circuit is electrically connected to the first end of each of the plurality of data lines. The first driving circuit is electrically coupled to first ends of the plurality of data lines, a first end of the end data line is electrically coupled to a first end of the start data line, and the second driving circuit is electrically coupled to second ends of the plurality of data lines.

Array substrate and display device

An array substrate and a display panel are described. The array substrate may include a first base; a plurality of pixel units arrayed on the first base in a row direction and a column direction; each of the pixel units comprising at least two sub-pixels arranged in the row direction; a plurality of first scanning lines sequentially arranged on the first base in the column direction, at least one first scanning line being arranged at a side of each row of pixel units in the column direction, the first scanning lines being connected with the sub-pixels; and a plurality of second scanning lines sequentially arranged on the first base in the row direction, at least one second scanning line being arranged at a side of each column of pixel units in the row direction.

Array substrate and display panel

The present disclosure relates to the field of display technology, and in particular, to an array substrate and a display apparatus. The array substrate has a display area and a peripheral wiring area provided at at least one side of the display area. The display area includes a thin film transistor and a common electrode formed on the base substrate; the peripheral wiring area includes a first lead, a gate signal line and a common signal line formed on the base substrate; the first lead and the gate electrode of the thin film transistor are arranged in an identical layer and are electrically connected; the gate signal line is located on a side of the first lead away from the base substrate, and is electrically connected to the first lead through a first transition structure.

Array substrate and display apparatus

A display panel and a display device are disclosed. The display panel comprises an array substrate and spacers; the array substrate comprises a first substrate, gate lines, data lines, and multiple sub-pixel units; the first substrate is provided with multiple sub-pixel regions, first wiring regions each located between two adjacent rows of sub-pixel regions, and second wiring regions each located between two adjacent columns of sub-pixel regions and intersecting the first wiring regions; at least part of each sub-pixel unit is located on a sub-pixel region; the gate lines and the data lines are respectively located on the first wiring regions and the second wiring regions and are electrically connected to the sub-pixel units; the data lines and the gate lines are insulated from each other and intersect each other; each data line is provided with an alignment part.

The present invention relates to a touch display device, a drive control circuit for the touch display device, and a method for operating the touch display device. The touch display device includes a drive control circuit, the drive control circuit is configured to: in a display phase, provide a common voltage signal to a common electrode in a pixel circuit of the touch display device; in a touch phase, provide a touch drive signal to the common electrode, wherein a ratio of an average value of a high level and a low level of the touch drive signal to a value of the common voltage signal ranges from 0.8 to 1.2.

Touch display device and method of operating the touch display device

Provided are a display panel and a display apparatus. The display panel comprises: a first substrate and a second substrate that are arranged opposite each other, wherein a display area and a frame area surrounding the display area are provided between the second substrate and the first substrate; a color resistance structure that is located in the frame area on the side of the second substrate facing the first substrate and surrounds the display area, wherein the color resistance structure comprises a first black matrix and a first color resistance portion arranged in a stacked manner; and a plurality of support bars that surround the display area, wherein each of the support bars fills a space between the color resistance structure and the first substrate.

Display panel comprising a plurality of support bars having ends that sequentially decrease in length in a direction from a frame area to a display area and display apparatus

The present disclosure relates to an array substrate and a display device. The array substrate may include: a first substrate, and a plurality of pixel groups and a plurality of columns of data lines formed on the first substrate; wherein the plurality of pixel groups are arranged in an array along a row direction and a column direction, and each pixel group includes two sub-pixels arranged in the row direction; at least one sub-pixel of one of any two adjacent pixel groups in the row direction corresponds to the same color as one sub-pixel of the other pixel group; and any two adjacent sub-pixels in the row direction correspond to different colors; and each column of data line and each column of pixel groups are alternately arranged in the row direction.

An array substrate includes a base substrate, pixel electrodes and common electrodes, first scan lines, second scan lines and data lines. The pixel electrode has first electrode strips disposed at intervals in a row direction. The common electrodes and the pixel electrodes are disposed on the same layer, and the common electrodes have second electrode strips disposed at intervals. The second electrode strips and the first electrode strips are alternatively arranged. The first scan line is located between two adjacent rows of pixel electrodes. The second scan line is located between two adjacent columns of pixel electrodes and is electrically connected to the first scan line, and the second scan line has a scan signal input terminal. The data line has a data signal input terminal. An orthographic projection of the data line on the base substrate intersects with a central region of the pixel electrode on the base substrate.

The present disclosure provides a display panel and a display device. The display panel includes p pixel unit groups, and each of the p pixel unit groups includes q rows of pixel units, both p and q being integers greater than or equal to 2. Pixel units in a same group are simultaneously supplied with a gate scan signal by a same shift register, and pixel units in a same group and in a same column are supplied with data voltage signals through different data lines, respectively.

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Beijing, China

Zhihua Sun