No. 24 Research Institute of China Electronics Technology Group Corporation

Zhihua Feng

Dongbing Fu

Guangbing Chen

Jian'an Wang

Ruzhang Li

Gangyi Hu

Tao Liu

Daiguo Xu

Jie Pu

Shiliu Xu

The present disclosure provides a high-speed and low-noise dynamic comparator, which includes: an input unit, including an input NMOS transistor and an input PMOS transistor; a latch unit, including a latching NMOS transistor and a latching PMOS transistor, where the latching NMOS transistor and the latching PMOS transistor are connected to form a latch structure; a pull-up unit, including a pull-up PMOS transistor connected to the input NMOS transistor; and a substrate bootstrap voltage generation circuit, generating a substrate bootstrap voltage. In the present disclosure, a substrate bootstrap technology of MOS transistors is used, thereby reducing on resistances of the MOS transistors and improving the comparator speed; threshold voltages of the input transistors of the comparator are reduced, transconductance of the input transistors is increased, thereby reducing equivalent input noise of the comparator, and as a common-mode voltage of the comparator changes, a comparison delay changes relatively little.

High-speed and low-noise dynamic comparator

Growing community of inventors

Chongqing, China

Zhihua Feng