The Mathworks, Inc.

Zhihong Zhao

Partha Biswas

Vijay Raghavan

Vijaya Raghavan

Beth Cockerham

Aditya Agrawal

Ramamurthy Mani

Brian Keith Ogilvie

Hidayet Tunc Simsek

Yongfeng Gu

Rajiv Ghosh-Roy

Wang Chen

Katalin Maria Popovici

Donald Paul Orofino, Ii

Sankalp Sandeep Modi

Charles J Devane

Bharath Venkataraman

A device is configured to receive delay information associated with a model including a set of model elements and one or more delay elements. The delay information may identify a model element, of the set of model elements, and a quantity of delay to be associated with the model element. The model may be associated with a total quantity of delay. The device is configured to determine accumulated delay information based on the model, and to determine a set of retiming values associated with the set of model elements. The device is configured to redistribute the one or more delay elements associated with the model, based on the set of retiming values, to satisfy the quantity of delay to be associated with the model element, and to maintain the total quantity of delay associated with the model. The device is configured to provide the redistributed model.

User-constrained delay redistribution

In an embodiment, a system may receive information regarding a group of physical devices; receive information regarding a set of functional blocks associated with a functional model; and receive mapping information that indicates a mapping between the set of functional blocks and one or more physical devices of the group of physical devices. The system may further generate at least one functional effect associated with the functional model. The generating may be based on: the set of functional blocks, the mapping information, and the information regarding the one or more physical devices. The system may also store or output the at least one functional effect.

Automatic modeling, mapping, and code generation for homogeneous and heterogeneous platforms

A system and method evaluates power information for a high-level model to be implemented in target hardware, and performs one or more power-reducing transmutations on the model. Transmutations may include moving one or more components from a fast rate region to a slow rate region, reducing bit width of data, signals, or other values, and replacing multiple instances of a resource with a shared instance of the resource. An in-memory representation of the model may be generated that reduces the model to a plurality of core components. A power score evaluation engine may assign power scores to the core components. Power scores may be retrieved from one or more power score database. The power scores may be non-dimensional scores representing power consumption relationships among the core components, and be target independent. Hints or alerts regarding suggested changes to the model to optimize power consumption may be presented to a user. A revised model incorporating the suggested changes may be constructed. The one or more transmutations resulting in a lowest total power score may be selected for hardware generation.

Model level power consumption optimization in hardware description generation

A device is configured to receive optimization information associated with a model, determine an amount of delay to be inserted into the model, and determine a sampling factor by which a first data rate associated with a signal is to be modified into a second data rate. The device is configured to determine a region of interest, insert an upsampling block that upsamples the signal entering the region of interest based on the sampling factor, and insert a downsampling block, associated with a unit of delay, which downsamples the signal exiting the region of interest based on the sampling factor. The device is configured to convert the unit of delay into a fast delay block, corresponding to the amount of delay, and insert the fast delay block in the region of interest. The device is configured to generate code associated with the model, and provide the code.

Code generation based on regional upsampling-based delay insertion

A device receives information associated with a functional model, and generates the functional model based on the received information and with a technical computing environment (TCE), where the functional model including nodes, inputs, and outputs. The device also automatically detects architecture information from an architecture model associated with the functional model, and automatically assigns, based on the architecture information, at least one signal between two nodes of the functional model, a node and an input of the functional model, or a node and an output of the functional model. The device obtains information for code generation based on the assigned at least one signal, and stores the information for code generation.

Automatic assignment of signals for a functional model

A system and method automatically inserts pipelines into a high-level program specification. An Intermediate Representation (IR) builder creates one or more graphs or trees based on the high-level program specification. A scheduler iteratively applies a bounded scheduling algorithm to produce an execution schedule for the IR minimizing overall execution time for a given number of pipeline stages. A Hardware Description Language (HDL) code generator may utilize the pipelined, scheduled IR to generate optimized HDL code corresponding to the high-level program specification. An annotated version of the high-level program specification showing where the pipelines have been inserted may be displayed allowing additional design exploration.

Auto pipeline insertion

Methods, systems and computer program products are disclosed for automatically generating hardware description language code from a model. The hardware description language code may be generated from a graphical program/model, such as a block diagram model. The hardware description language code may also be generated from a text-based program/model, such as a model created using MATLAB&#xae; tools. In particular, the present invention provides for the automatic code generation of an interface between components in the model. The present invention may provide options for selecting at least one of multiple types or styles of the component interfaces in the model. The selection of the interface types or styles may be controlled by the user or inferred by other parameters, such as implementation parameters.

Automatic generation of code for component interfaces in models

Technique for automatically assigning placement for pipeline registers within code generated from a program specification

A system generates a state diagram model in a graphical modeling system, where the state diagram model includes at least one state. A condition statement is associated with the at least one state, and defines a condition upon which one or more actions associated with the at least one state are executed.

Conditionally executed states

The present invention provides a state diagramming environment in a computing device that enables the conversion of a state diagram into a hardware description language. To achieve this conversion, the present invention generates an intermediate representation of the state diagram. The intermediate representation is checked against a set of predefined restrictions for compliance. The state diagramming environment converts the intermediate representation of the state diagram into a hardware description language, such as VHDL or Verilog.

Hardware description language code generation from a state diagram

Methods and systems for providing a synchronous model in a modeling environment are disclosed. The predetermined operations of the model, such as a transition to a state in a state-based modeling environment, are implicitly synchronized with a signal selected by users, such as a clock signal. The predetermined operations of the model may be synchronized on a rising and/or falling edge of the clock signal. The synchronization of the operations is guarded in which the predetermined operation of the model occurs only on the synchronization signal selected by the users while other operations may occur at any time when the model is activated.

Synchronous models in modeling environments

The present invention provides a user of a state diagramming environment with the ability to specify if the user wants to develop a Moore machine or a Mealy machine. To achieve this, a set of predefined requirements is provided that restricts the state diagram semantics to either semantics of a Moore or Mealy machine. When a user provides a state diagram that does not conform to the set of requirements, the state diagram is identified as non-conforming and the user is notified of the non-conformance. The user is given information describing what aspects of the state diagram do not conform, thereby, allowing the user to quickly identify any errors that have been made. As a result of the present invention, the burden placed on the user is reduced and the time spent debugging is minimized.

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Newton, MA, United States of America

Zhihong Zhao