Texas Instruments Corporation

Zhihong You

Liming Xiu

Joseph A Devore

John H Carpenter, Jr

Benjamin Lee Amey

Brett Jason Thompsen

Systems, methods and circuits for regulator minimum load control. In one particular case, a system is provided that includes a load control circuit and a switched load. The load control circuit includes a reference current, and a sense current representative of a load current. In addition, the load control circuit includes a comparator circuit that drives a control signal in response to a comparison between the reference current and the sense current. The switched load is electrically coupled to a load voltage signal to provide loading to the load voltage signal. The switched load is operable to switch between a first loading factor and a second loading factor in response to the control signal.

Circuits, devices and methods for regulator minimum load control

A clock synthesis circuit) including a phase-locked loop and one or more frequency synthesis circuits is disclosed. The phase-locked loop includes a voltage-controlled oscillator (VCO) having a sequence differential stages o produce equally spaced clock phases. The frequency synthesis circuit includes a sequence of adder-and-register units that select one of the VCO clock phases. An output multiplexer receives each of the selected clock phases, and selects among these clock phases in sequence; the output of the multiplexer is applied to a first toggle flip-flop that changes state in response to rising edge transitions at the output of the multiplexer. A second toggle flip-flop is clocked by the output of the first toggle flip-flop, itself toggling in response to rising edge transitions at the output of the first toggle flip-flop. One or more additional flip-flops can be similarly connected in sequence. The additional toggle flip-flop enables the VCO to be formed with fewer stages for a given frequency resolution, reducing noise and thus frequency error.

Precision frequency and phase synthesis with fewer voltage-controlled oscillator stages

An electronic system () includes a phase-locked loop () and a frequency synthesis circuit (), for generating a jitter-free output clock (CLKCLK) at a desired frequency. The phase-locked loop () includes a voltage-controlled oscillator () that produces a number (N) of equally spaced clock phases at a frequency (f) that depends also upon a programmable feedback frequency divider () and a prescale divider (). The frequency synthesis circuit () generates the output clock (CLKCLK) at a frequency under the control of a frequency select word (FREQ) that indicates the number of clock phases between successive clock edges. A central processing unit (), either itself or from a look-up table (), generates a feedback divide integer (M) and the frequency select word (FREQ) according to a desired frequency (f), by way of a minimization of the frequency error. The frequency of the output clock (CLKCLK) can be generated in a jitter-free manner, since only integer values are used in the frequency synthesis circuit (), at relatively low frequency error.

Precision jitter-free frequency synthesis

A clock synthesis circuit () including a phase-locked loop () and one or more frequency synthesis circuits () is disclosed. A disclosed implementation of the phase-locked loop () includes a voltage-controlled oscillator () having an even number of differential stages () to produce an even number of equally spaced clock phases. In one arrangement, the frequency synthesis circuit () includes two adder legs that generate select signals applied to first and second multiplexers (), for selecting among the clock phases from the voltage-controlled oscillator (). The outputs of the first and second multiplexers () are applied to a two-to-one multiplexer () which is controlled by the output clock signal (CLK), to drive clock edges to a T flip-flop () to produce the output clock signals (CLK, CLK). In another embodiment, more than two adder and register units () control corresponding multiplexers () for selecting clock phases from the voltage-controlled oscillator () for application to an output multiplexer (), which is controlled by a clock control circuit () to apply the selected clock phases to the T flip-flop (). In another embodiment, primary and phase-shifted frequency synthesis circuits () receive initialization values (INIT, INIT) that establish the phase differential and ensure proper initialization.

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Plano, TX, United States of America

Zhihong You