Globalfoundries Singapore Pte. Ltd.

Zhihong Luo

Benjamin Shui Chor Lau

Yi Liang

Bai Yen Nguyen

Qi Chen

Fei Xu

Benjamin Lau

Xiaobo Qiu

Yeung On Au

On Au Yeung

Chun Huat Heng

Yong Lian

On Auyeung

Joanne Jinling Wang

Swee Chuen Hoo

Swee Chen Hoo

Sui Chor Benjamin Lau

Integrated circuits including semiconductor memory devices, read assist circuits for semiconductor memory devices, and methods for operating such circuits are provided. In an embodiment, a read assist circuit for use in a semiconductor memory device is provided. The read assist circuit includes a first drive device for driving a wordline of the semiconductor memory device to a wordline driving voltage. The first drive device operates at a first current. The read assist circuit also includes a second drive device for maintaining the wordline of the semiconductor memory device at the wordline driving voltage. The second drive device operates at a second current lower than the first current.

Integrated circuits with SRAM devices having read assist circuits and methods for operating such circuits

Device and a method of configuring a voltage level shifter is disclosed. The device includes a traditional level shifter circuit (TLSC), a first control circuit (FCC) cross-coupled to a second control circuit (SCC). The FCC is coupled to receive an inverse of an input at a first input node and provide a first output at a first output node. The SCC is coupled to receive the input at a second input node and provide a second output at a second output node and the TLSC is configured to provide an output at an output node in response to the first output received at the first output node and the second output received at the second output node. A first power source is configured to provide a first power supply voltage to the TLSC, the FCC and the SCC. The output is latched to track the input. The TLSC, the FCC and the SCC are coupled to a ground reference node.

Wide range level shifter for low voltage input applications

Redundant inverters with multiple inverter stages enable lower operating voltages to be used. For example, the use of multiple inverter stages produces a strong '0' or a strong '1' output signal. The strong output signal facilitates self-oscillation of a ring oscillator at lower voltages.

Ultra low voltage ring oscillator with redundant inverter

A digital controlled oscillator (DCO) is provided that includes a plurality of selectable delay cells, a first load adjustment delay (LAD) cell, a second LAD cell, a first set of the load cells (LCs), a second set of the LCs and first and second capacitance elements. A number of the selectable delay cells that are part of a delay cell chain is configurable based on a delay cell number control vector. The delay cell chain generates a delay cell output signal that is received by the first LAD cell. The first set of the LCs generate a first load signal to control an amount of loading on the second LAD cell, and the second set of the LCs generate a second load signal to control loading on the first LAD cell. Substrate voltages of the first and second capacitance elements can be adjusted to adjust loading in the DCO.

Digitally controlled oscillator (DCO) for a phase locked loop (PLL) system

A PLL control system is provided that implements a phase tracer module to reduce lock time and output clock jitter. A second clock signal is generated by dividing a frequency of a reference clock signal. A feedback clock signal is generated based on a high-frequency clock signal from a digitally controlled oscillator (DCO) and a PLL feedback divide number. Lead/lag determination circuitry generates a lead/lag detection result that indicates whether the feedback clock signal leads or lags the second clock signal. A skew digitizer digitizes a skew between a falling edge of the second clock signal and a rising edge of the feedback clock signal to generate a skew signal. The phase tracer module processes the lead/lag detection result and the skew signal to generate a digital control signal that controls cycle time of the DCO to change frequency of the high-frequency clock signal.

Digital phase locked loop (PLL) system and method with phase tracing

A phase locked loop (PLL) control system is provided that includes a digital controlled oscillator (DCO). The DCO comprises a delay cell chain comprising a number (B) of delay cells, and a load control cell comprising a number (L) of load cells. A system also includes that module that is configured to dynamically adjust the number (B) of delay cells that are activated and part of the delay cell chain and the number (L) of load cells that are switched on, when the PLL control system is operating in a lock mode, to control an amount of delay in the DCO.

Digital phase locked loop (PLL) system with frequency band jump in lock mode

A fuse circuit having a fuse unit cell containing two fuses. In the program/write mode, only one of the fuses in the fuse unit cell will be blown. In read mode, since only one fuse is blown, the current that goes through the two fuses in the fuse unit cell will be very small. Hence, the read power consumption for the fuse circuit is also very small and its sensing speed is also very high.

High speed low power fuse circuit

A fuse sensing circuit is disclosed. Embodiments include: providing a sense input terminal; providing a sense output terminal; and providing first and second capacitors that are configured to charge and discharge based on the sense input terminal, wherein the first and second capacitors are further configured to discharge current to a fuse unit cell, and the sense output terminal is configured to indicate a fuse state of the fuse unit cell based on the discharging of the first and second capacitors. Embodiments include the indicated fuse state being based on a discharge rate difference between the discharging of the first capacitor and the discharging of the second capacitor.

Fuse sensing circuits

A phase locked loop control system includes a digital controlled oscillator (DCO) that is controlled by logic cells in response to comparison of the oscillator output with a reference clock related signal. Delay cell number adjustment, delay cell load adjustment and cycle control are operative to digitally control the DCO frequency to obtain wide frequency range and limited jitter.

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Singapore, Singapore

Zhihong Luo