Cadence Design Systems, Inc.

Proplus Design Solutions, Inc.

Other

Proplus Electronics Co., Ltd.

Jinan Proplus Electronics Co., Ltd.

Primarius Technologies Co., Ltd.

Zhihong Liu

Bruce W McGaughy

Lifeng Wu

Xisheng Zhang

Hancheng Liang

Yutao Ma

Jianhe Guo

Jeong Yeol Choi

Ping F Chen

Alvin Chen

Jingkun Fang

Nobufusa Iwanishi

James Chieh-Tsung Chen

Yoshiyuki Kawakami

Hirokazu Yonezawa

Jushan Xie

Norio Koike

Gang Zhang

Chune-Sin Yeh

Kwok Kwong Hung

Xucheng Pang

Alvin I-Hsien Chen

Min-Che Jeng

Min-Chie Jeng

Method and System for Parallel Design and Technology Optimization are disclosed. The disclosed method enables efficient parallel design and technology optimization (PDTO) and allow designers to sign off the technology development or find the optimal design point with the design analysis tools. The method includes generating, from a manufacturing technology process, a baseline SPICE model based on technology specification and manufacturing process data; extending the baseline SPICE model to a corresponding description of technology specification window in the circuit design process, where the technology specification window describes extended ranges of device model parameters; extracting a targeted SPICE model using the technology specification window; verifying, by a circuit design process that operates in parallel to the manufacturing technology process, the integrated circuit meets a design specification using the targeted SPICE model.

Method and system for parallel design and technology optimization

Apparatuses of a noise measurement system and methods for using the same are disclosed. In one embodiment, a noise measurement system may include a plurality of probe groups electrically coupled to a plurality of DUTs, where a probe group in the plurality of probe groups includes multiple channels, and where the multiple channels of each probe group are bundled as a group for reducing electromagnetic interference among the plurality of probe groups, and wherein the group is shielded from corresponding signal groups of other DUTs with a connection to a circuit ground of the noise measurement system for reducing ground loop generated signal interference. The noise measurement system may further include a controller configured to perform noise measurement.

Noise measurement system

Embodiments of apparatuses of a synchronized noise measurement system and methods for using the same are disclosed. In one embodiment, a method of performing noise measurement includes setting up a plurality of device under tests (DUTs), performing noise measurement of the plurality of DUTs synchronously using programmable testing parameters to generate a noise measurement data, collecting the noise measurement data from the plurality of DUTs in parallel, and analyzing the noise measurement data collected to identify deviations in noise performance caused by manufacturing process variations or environmental variations for the plurality of DUTs.

Synchronized noise measurement system

Apparatuses and methods for measuring flicker noise are disclosed. In one embodiment, a noise measurement system may include a first circuit path configured to drive a first terminal of a device under test (DUT) in the noise measurement system, a charging circuit path configured to charge the first terminal of the DUT in a setup phase, and logic configured to charge the first terminal of the DUT to a predetermined voltage using the first circuit path and the charging circuit path in the setup phase.

Apparatuses and methods for measuring flicker noise are disclosed. In one embodiment, a noise measurement system may include a first circuit path configured to drive a first terminal of a device under test (DUT) in the noise measurement system, an amplification circuit configured to amplify an output signal of the DUT, a second circuit path configured to drive a second terminal of the DUT, a third circuit path configured to couple a third terminal of the DUT to a circuit ground, and a decoupling circuit configured to decouple the DUT and the amplification circuit, logic configured to detect output signal characteristics of the DUT, logic configured to adjust input impedance of the amplification circuit based on the output signal characteristics of the DUT, and logic configured to measure a flicker noise of the DUT using the amplification circuit with adjusted input impedance.

Apparatuses and methods for measuring flicker noise

Method and system are disclosed for repetitive circuit simulation. In one embodiment, a computer implemented method for performing multiple simulations of a circuit includes providing descriptions of connectivity, instants, signal activities, and statistical parameters of the circuit, parsing the circuit in accordance with the descriptions of connectivity, instants, signal activities, and statistical parameters of the circuit to form one or more circuit partitions, performing a first pass simulation of the one or more circuit partitions in accordance with a set of stimuli to generate a history of the first pass simulation, and performing subsequent simulation of the one or more circuit partitions using the history of the first pass simulation.

Repetitive circuit simulation

Method and system are disclosed for modeling dynamic behavior of a transistor. The method includes representing static behavior of a transistor using a lookup table, selecting an instance of the transistor from the lookup table for modeling dynamic behavior of the transistor, computing a previous state of the instance using a non-quasi static analytical model, computing a variation in channel charge of the instance according to a rate of change in time, computing a current state of the instance using the previous state and the variation in channel charge, computing a modified terminal voltage that includes a dynamic voltage across a parasitic resistance at the terminal of the transistor according to the current state and previous state of the instance, and storing the modified terminal voltage in a memory device for modeling dynamic behavior of the transistor at the current state.

Method and system for simulating dynamic behavior of a transistor

The present invention is directed to a number of improvements in methods for reliability simulations in aged circuits whose operation has been degraded through hot-carrier or other effects. A plurality of different circuit stress times can be simulated within a single run. Different aging criteria may be used for different circuit blocks, circuit block types, devices, device models and device types. The user may specify the degradation of selected circuit blocks, circuit block types, devices, device models and device types independently of the simulation. Device degradation can be characterized in tables. Continuous degradation levels can be quantized. Techniques are also described for representing the aged device in the netlist as the fresh device augmented with a plurality of independent current sources connected between its terminals to mimic the effects of aging in the device. The use of device model cards with age parameters is also described. To further improve the circuit reliability simulation, a gradual or multi-step aging is used instead of the standard one step aging process. Many of these features can be embedded within the circuit simulator. A user data interface is also presented to implement these techniques and further allow users to enter their device models not presented in the simulator. For example, a proprietary model of, say, the substrate current in an NMOS could used be with a SPICE simulator employing a different model to simulate the aging of the circuit.

Hot carrier circuit reliability simulation

The present invention presents methods for modeling the high frequency and noise characterization of MOSFETs. The models may be readily implemented as part of a SPICE or other simulation in a design flow. In particular, this invention is capable of providing a sub-circuit representation of a MOSFET that can accurately predicate a MOSFET's low frequency, high frequency, and noise characterizations. An interface is described through which a user may simultaneously optimize all of these characterizations. Further, methods are presented for building models that can predicate the variations in MOSFETs due to manufacturing processes and generate a corresponding corner model.

MOSFET modeling for IC design accurate for high frequencies

A solution of a first set of equations of the time-varying electrical response of a circuit is determined between pairs of adjacent time points tand tbased on predicted electrical responses of the devices at time point tand as a function of the initial temperatures of the circuit devices at time point t. A solution of a second set of equations of the time-varying temperature responses of devices of the circuit is determined (1) after each iteration of the first set of equations and as a function thereof or (2) at each time point tand as a function of the solution of the first set of equations at the time point to determine the corresponding temperature response of the circuit. The solutions of the first and second sets of equations at one or more of the points in time are displayed.

Circuit simulation with decoupled self-heating analysis

The present invention is directed to a number of improvements in methods for hot-carrier device degradation modeling and extraction. Several improvements are presented for the improvement of building device degradation models, including allowing the user to select a device parameter used to build the device degradation model independent of the device parameter selected. The user can also select the functional relation between stress time and degradation level. To further improve accuracy, multiple acceleration parameters can be used to account for different regions of the degradation process. Analytical functions may be used to represent aged device model parameters, either directly or by fitting measured device parameters versus device age values, allowing devices with different age values to share the same device model. The concept of binning is extended to include device degradation. In addition to a binning based on device width and length, age is added. In an exemplary embodiment, only devices with minimum channel length have degraded models constructed. The present invention also allows the degradation of one device parameter to be determined based on an age value derived from another parameter. In yet another aspect, a degraded device is modeled as a fresh device with a voltage source connected to a terminal.

Hot-carrier device degradation modeling and extraction methodologies

The present invention includes a method for detecting model stamping errors during circuit simulation without the need for golden data. The method checks for model stamping errors by determining whether entries in model stamping matrices interrelate according to a plurality of preset rules before circuit equations are solved.

Model stamping matrix check technique in circuit simulator

The present invention includes a method for modeling devices having different geometries, in which a range of interest for device geometrical variations is divided into a plurality of subregions each corresponding to a subrange of device geometrical variations. The plurality of subregions include a first type of subregions and a second type of subregions. The first or second type of subregions include one or more subregions. A regional global model is generated for each of the first type of subregions and a binning model is generated for each of the second type of subregions. The regional global model for a subregion uses one set of model parameters to comprehend the subrange of device geometrical variations corresponding to the G-type subregion. The binning model for a subregion includes binning parameters to provide continuity of the model parameters when device geometry varies across two different subregions.

Growing community of inventors

Cupertino, CA, United States of America

Zhihong Liu