The 13Th Research Institute of China Electronics Technology Group Corporation

The 13Th Research Institute of China Electronics

The 13ᵗʰ Research Institute of China Electronics Technology Group Corporation

The 13Th Research Institute of China Electronics Technolegy Group Corporation

The 13Th Research Institute of China Electronics Technology

Zhihong Feng

Yuanjie Lv

Yuangang Wang

Xubo Song

Xingye Zhou

Xin Tan

Shixiong Liang

Yulong Fang

Zezhao He

Jia Li

Jingjing Wang

Qingbin Liu

Cui Yu

Chuangjie Zhou

Shaobo Dun

Hongyu Guo

Xingchang Fu

Bo Wang

Xuefeng Zou

Cui Wei

Yanmin Guo

Hongyu Liu

Zhirong Zhang

Jianchao Guo

Xuedong Gao

Junlong Wang

Dabao Yang

Lisen Zhang

Xiangyang Zhao

Dong Xing

Tingting Han

Peng Xu

Weili Lu

Guodong Gu

Jiayun Yin

Shujun Cai

A ultraviolet detector includes a substrate; a first epitaxial layer that is a heavily doped epitaxial layer and located on the substrate, a second epitaxial layer located on the first epitaxial layer, where the second epitaxial layer is a lightly doped epitaxial layer, or a double-layer or multi-layer structure composed of at least one lightly doped epitaxial layer and at least one heavily doped epitaxial layer; an ohmic contact layer located on the second epitaxial layer or formed in the second epitaxial layer, where the ohmic contact layer is a graphical heavily doped layer; and a first metal electrode layer located on the ohmic contact layer.

Ultraviolet detector and preparation method therefor

The disclosure provides a preparation method of GaN field effect transistor based on diamond substrate, and relates to the technical field of semiconductor manufacturing. The method includes the following steps: preparing a GaN heterojunction layer on the front-side of a SiC substrate; thinning the SiC substrate; etching the SiC substrate; growing a diamond layer; removing a sacrificial layer and the diamond layer on the sacrificial layer; preparing a source electrode, a drain electrode and a gate electrode on the front surface of the GaN heterojunction layer; etching the SiC substrate and the GaN heterojunction layer to form a source through hole communicated with the source electrode; and removing the through hole mask layer, and preparing back grounding metal to complete the preparation of the diamond substrate GaN transistor device.

Preparation method of GaN field effect transistor based on diamond substrate

A gallium oxide Schottky barrier diode with negative beveled angle terminal and a production method thereof are provided. The production method includes four steps. In the first step, a photoresist layer with a preset pattern is formed on a gallium oxide epitaxial layer, where the gallium oxide epitaxial layer is formed on an upper surface of a gallium oxide substrate. In the second step, first electrode layer is formed on the gallium oxide epitaxial layer. In the third step, the gallium oxide substrate is rotated and the gallium oxide epitaxial layer is etched. In the fourth step, a second electrode layer is formed on the lower surface of the gallium oxide substrate.

Method for producing gallium oxide Schottky barrier diode with negative beveled angle terminal

The disclosure provides a normally-off gallium oxide field-effect transistor structure and a preparation method therefor, and relates to the technical field of semiconductor device. The normally-off gallium oxide field-effect transistor structure comprises a substrate layer and an n-type doped gallium oxide channel layer from bottom to top. The n-type doped gallium oxide channel layer is provided with a source, a drain, and a gate. The gate is located between the source and the drain. A no-electron channel region is provided in the n-type doped gallium oxide channel layer located below the gate.

Normally-off gallium oxide field-effect transistor structure and preparation method therefor

The disclosure is applicable for the technical field of semiconductor devices manufacturing, and provides a gallium oxide SBD terminal structure. The gallium oxide SBD terminal structure comprises a cathode metal layer, an Nhigh-concentration substrate layer, an Nlow-concentration GaOepitaxial layer and an anode metal layer from bottom to top, wherein the Nlow-concentration GaOepitaxial layer is within a range of certain thickness close to the anode metal layer; and a doping concentration below the anode metal layer is greater than a doping concentration on two sides of the anode metal layer. Namely, only a doping concentration of the part outside the corresponding area of the anode metal layer is changed, so that the breakdown voltage of the gallium oxide SBD terminal structure is improved under the condition of guaranteeing low on resistance.

Gallium oxide SBD terminal structure and preparation method

The disclosure is related to the technical field of semiconductors, and provides a method for manufacturing a tilted mesa and a method for manufacturing a detector. The method for manufacturing a tilted mesa comprises: coating a photoresist layer on a mesa region of a chip; heating the chip on which the photoresist layer is coated from a first preset temperature to a second preset temperature; performing etching processing on the heated chip, so as to manufacture a mesa having a preset tilting angle; and removing the photoresist layer on the mesa region of the chip after the mesa is manufactured.

Method for manufacturing tilted mesa and method for manufacturing detector

A method for preparing an avalanche photodiode includes preparing a mesa on a wafer, growing a sacrificial layer on an upper surface of the wafer and a side surface of the mesa, removing the sacrificial layer in an ohmic contact electrode region of the wafer, preparing an ohmic contact electrode in the ohmic contact electrode region of the wafer, removing the sacrificial layer in a non-mesa region of the wafer, growing a passivation layer on the upper surface of the wafer and the side surface of the mesa, removing the passivation layer on the upper surface of the mesa of the wafer and the passivation layer in the non-mesa region of the wafer corresponding to the ohmic contact electrode region, and removing the sacrificial layer on the upper surface of the mesa of the wafer.

Method for preparing avalanche photodiode

The disclosure provides a silicon carbide detector and a preparation method therefor. The silicon carbide detector comprises: a wafer, the wafer sequentially comprises, from bottom to top, a substrate, a silicon carbide P+ layer, an N-type silicon carbide insertion layer, an N+ type silicon carbide multiplication layer, an N-type silicon carbide absorption layer and a silicon carbide N+ layer; the doping concentration of the N-type silicon carbide insertion layer gradually increases from bottom to top, and the doping concentration of the N-type silicon carbide absorption layer gradually decreases from bottom to top; a mesa is etched on the wafer, and the mesa is etched to an upper surface of the silicon carbide P+ layer; an N-type electrode is arranged on an upper surface of the mesa, and a P-type electrode is arranged on an upper surface of a non-mesa region.

Silicon carbide detector and preparation method therefor

The present disclosure discloses a method for preparing an isolation area of a gallium oxide device, the method comprising: depositing a mask layer on a gallium oxide material; removing a preset portion region of the mask layer; preparing an isolation area in a position, corresponding to the preset portion region, on the gallium oxide material by using a high-temperature oxidation technique, with the isolation area being located between active areas of the gallium oxide device; and removing the remaining mask layer on the gallium oxide material. In the disclosure, the isolation area is prepared by using the high-temperature oxidation technique, which prevents damage to the gallium oxide device during the preparation of the isolation area, thereby achieving isolation between the active areas of the gallium oxide device.

Method for preparing isolation area of gallium oxide device

The disclosure provides a method for preparing a self-aligned surface channel field effect transistor, and provides a power device. The method includes the following steps: depositing a first metal mask layer; preparing a first photoresist layer; forming a source area pattern and a drain area pattern; depositing a source metal layer and a drain metal layer on the source area pattern and the drain area pattern; peeling off and removing the first photoresist layer; depositing a second metal mask layer; preparing a second photoresist layer, and forming at least one gate area pattern closer toward the source metal layer by performing exposure and development; removing the first metal mask layer and the second metal mask layer between the source metal layer and the drain metal layer by a wet corrosion; depositing a gate metal layer on the gate area pattern; and peeling off and removing the second photoresist layer.

Method for preparing self-aligned surface channel field effect transistor and power device

The disclosure provides a method for passivating a silicon carbide epitaxial layer, relating to the technical field of semiconductors. The method includes the following steps: introducing a carbon source and a silicon source into a reaction chamber, and growing a silicon carbide epitaxial layer on a substrate; and turning off the carbon source, introducing a nitrogen source and a silicon source into the reaction chamber, and growing a silicon nitride thin film on an upper surface of the silicon carbide epitaxial layer. The silicon nitride thin film grown by the method has few defects and high quality, and may be used as a lower dielectric layer of a gate electrode in a field effect transistor. It does not additionally need an oxidation process to form a SiOdielectric layer, thereby reducing device fabrication procedures.

Method for passivating silicon carbide epitaxial layer

The present disclosure discloses an enhancement-mode field effect transistor. This enhancement-mode field effect transistor includes a substrate, a channel layer formed on an upper surface of the substrate, a source electrode and a drain electrode respectively formed on both sides of the channel layer, and a gate electrode formed on an upper surface of the channel layer, a region outside the corresponding region of the gate electrode in the channel layer is provided with a carrier-free region. Carriers are absent in the carrier-free region, and carriers are present in the remaining portion of the channel layer. The carrier-free region is not disposed below the gate electrode, but is disposed outside the corresponding region of the gate electrode in the channel layer, and the threshold voltage of the device can be regulated by regulating the width and number of the carrier-free region.

Enhancement-mode field effect transistor

Disclosed are a preparation method for a diamond-based field effect transistor and a field effect transistor, relating to the technical field of semi-conductors. Said method comprising: forming a conductive layer on the upper surface of a diamond layer; the diamond layer being a high-resistance layer; manufacturing an active region mesa on the diamond layer; manufacturing, on the conductive layer, a source electrode on a first region corresponding to a source electrode region, and manufacturing, on the conductive layer, a drain electrode on a second region corresponding to a drain electrode region; depositing, on the conductive layer, a photocatalyst dielectric layer on the upper surface of a third region corresponding to a source and gate region, and depositing, on the conductive layer, the photocatalyst dielectric layer on the upper surface of a fourth region corresponding to a gate and drain region; illuminating the photocatalyst dielectric layer; depositing, on the conductive layer, a gate dielectric layer on a fifth region corresponding to gate electrode region, manufacturing a gate electrode on the upper surface of the gate dielectric layer. The present invention can reduce the on-resistance of devices.

Method for preparing diamond-based field effect transistor, and corresponding field effect transistor

An unbalanced terahertz frequency doubler circuit with power handling capacity is provided, and the circuit includes a RF input waveguide, a quartz substrate and a RF output waveguide, where one end of the quartz substrate is disposed in a waveguide groove of the RF input waveguide and the other end of the quartz substrate is disposed in a waveguide groove of the RF output waveguide, where an input transition microstrip is disposed on the quartz substrate, and one end of the transition microstrip is connected to an output transition microstrip sequentially through a first transmission microstrip, a low pass filter, a RF matching microstrip and a second transmission microstrip, where anodes of four GaAs-based terahertz frequency multiplier diode groups are connected to the RF matching microstrip, and a cathode at the outermost position of each of the GaAs-based terahertz frequency multiplier diode groups is connected to a grounding quartz strip.

Unbalanced terahertz frequency doubler circuit with power handling capacity

An enhanced HFET, comprising a HFET device body. Regions without two-dimensional electron gas are provided on a channel layer () at the portion between a drain electrode () and a source electrode () of the HFET device body, and there is a region without two-dimensional electron gas provided on the channel layer () at the portions excluding the area under a gate electrode (); two-dimensional electron gas regions are provided on the channel layer () excluding the portions located between the drain electrode () and the source electrode () and provided with the regions without two-dimensional electron gas; the channel layer () at the portion between the gate electrode () and the source electrode () and the portion between the gate electrode () and the drain electrode () are each provided with a two-dimensional electron gas region; and two-dimensional electron gas () is provided at a portion or whole portion of a two-dimensional electron gas layer at the channel layer () at the portion right under the gate electrode (). The HFET has the advantages of high saturation current, high threshold voltage controllability, fast response, low energy consumption, and the like.

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Shijiazhuang, China

Zhihong Feng