Texas Instruments Corporation

Zhihao Chen

Freidoon Mehrad

Brian Keith Kirkpatrick

Jon Holt

Jeff White

Suresh Potla

Edmund G Russell

Jason D Mehigan

Douglas Ticknor Grider

Shashank Sureshchandra Ekbote

Christoph A Wasshuber

Majid Movahed Mansoori

Brian M Trentman

Juanita Deloach

A trench structure in a wafer of semiconductor material and the method of forming the trench structure are described. The trench structure is formed on a semiconductor wafer that has a top surface of slow oxidization rate&#x2014;slower than that of other major crystallographic planes of the semiconductor material. The trench is etched into the semiconductor wafer. The trench has substantially vertical trench-sidewalls near the top surface, the vertical trench-sidewalls near the top surface containing crystallographic plane that oxidizes at a rate comparable to that of the top surface. An insulating layer is grown on the top surface and on the trench-sidewalls and on corners where sidewall surfaces approach the top surface, the insulating layer at the corners being substantially thicker than at the sidewall adjacent to the corners. The difference in the oxide thickness is due to the faster oxidizing planes exposed at the corners. Finally, the trench is filled with a dielectric material.

Method to form shallow trench isolation with rounded upper corner for advanced semiconductor circuits

Disclosed is a shallow trench isolation (STI) structure and methods of manufacturing the same. The methods eliminate the requirement for design size adjustments (DSA) in manufacturing the STI structure. Further disclosed is an STI trench liner and methods for the formation thereof by growing a thin oxide layer on shallow isolation trench surfaces while preventing oxide formation on adjacent nitride surfaces, followed by the deposition of, and oxide growth upon, a polysilicon layer.

Shallow trench isolation structure and method

A method of forming a flash memory array structure includes forming a first dielectric layer outwardly from a semiconductor substrate, removing a portion of the first dielectric layer and the substrate to create a trench isolation region, forming a second dielectric layer in the trench isolation region, removing a portion of the second dielectric layer to create an exposed substrate region proximate a bottom of the trench isolation region, doping the exposed substrate region with an n-type dopant, and forming a silicide region in the exposed substrate region.

Flash memory array structure and method of forming

A method of improving shallow trench isolation (STI) gap fill and moat nitride pull back is provided by after the steps of growing a pad oxide, depositing a nitride layer on the pad oxide and the steps of moat patterning, moat etching and moat clean, the steps of growing thermal oxide, deglazing a part of a part of the moat nitride; depositing a thin nitride liner, etching the nitride to form a thin side wall nitride in the STI trench; and performing an oxide Hydroflouric (HF) acid deglazing before STI liner oxidating and depositing oxide to fill the trench.

Method to improve STI nano gap fill and moat nitride pull back

A method of fabricating a shallow trench isolation structure includes forming outwardly of a semiconductor layer a first oxide layer. A nitride layer is formed outwardly of the first oxide layer. A second oxide layer is formed outwardly of the nitride layer. A trench is formed through the first oxide layer, the nitride layer, and the second oxide layer and into the semiconductor layer. With the second oxide layer protecting an upper surface of the nitride layer, the nitride layer is etched to form a lateral recessed side boundary of the trench at the nitride layer. The shallow trench isolation layer is formed in the trench.

Method for moat nitride pull back for shallow trench isolation

A method for isolating semiconductor devices includes forming a first oxide layer outwardly from a semiconductor substrate, forming a first nitride layer outwardly from the first oxide layer, removing a portion of the first nitride layer, a portion of the first oxide layer, and a portion of the substrate to form a trench isolation region, forming a second oxide layer in the trench isolation region, forming a spin-on-glass region in the trench isolation region, annealing the spin-on-glass region, removing a portion of the spin-on-glass region to expose a shallow trench isolation region, and forming a third oxide layer in the shallow trench isolation region.

Semiconductor device isolation structure and method of forming

Methods are disclosed for the formation of isolation structures and trenches in semiconductor devices, in which lower corners of an isolation trench are rounded after trench formation using an oxidation process which oxidizes substrate material from the trench sidewalls and bottom faster than from the lower corners of the trench. The oxide formed during the rounding process is then removed prior to performing other etch processes, to expose substrate material having rounded lower corners. Thereafter, a liner is formed and the trench is filled with dielectric material to complete the isolation structure.

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Plano, TX, United States of America

Zhihao Chen