Intel Corporation

Zhiguo Wang

Min Huang

Stefan Rusu

Bahaa Fahim

Krishnakanth Venkata Sistla

Baskaran Ganesan

David J Ayers

Srikanth Balasubramanian

William Johnson Bowhill

Eric Dehaemer

Stephen M Ramey

Joseph R Doucette

Vinod Ambrose

Harjinder Hullon

Seow Fung Ooi

Yin-Lung Lu

Sukirti Gupta

Joseph Doucette

Seow Ooi

A cache controller id disclosed, The cache controller includes circuitry to receive a request to access data in a target location of a last level cache of a processor on a processor package, identify an in-field failure in the target location of the last level cache, perform, in response to the identification of the in-field failure, an in-field repair, including circuitry to write in-field repair information to a non-volatile memory on the processor package and external to the processor, the non-volatile memory including circuitry to store in-field repair information. Systems and methods are also disclosed.

System and method for granular in-field cache repair

Systems and methods for granular cache repair. An example processing system comprises a processing core communicatively coupled to a cache via a cache controller and a cache repair memory communicatively coupled to the cache controller. The cache controller is configured, responsive to receiving a read request referencing a physical address, to: retrieve cache data from a cache location identified by the physical address, retrieve, in parallel with retrieving the cache data, cache repair data from the cache repair memory, the cache repair data associated with the cache location, the cache repair data comprising at least one of: a bit repair value, a column repair value, and a raw repair value, and output the cache data multiplexed with the cache repair data.

Granular cache repair

In an embodiment, a processor includes a plurality of cores grouped into a plurality of clusters. The clusters are formed based on a corresponding operating voltage of each core at each of a plurality of frequencies. Each cluster includes a unique set of cores and at least one cluster includes at least two of the cores. The processor also includes a power control unit (PCU) including frequency/voltage control logic, responsive to a frequency change request for a first core of a first cluster, to determine an operating voltage for the first core from a first cluster voltage-frequency (V-F) table associated with the first cluster. The first cluster V-F table uniquely specifies a corresponding operating voltage at each of a plurality of frequencies of operation of the cores of the first cluster. Other embodiments are described and claimed.

Apparatus and method to implement power management of a processor

In an embodiment, a processor includes voltage calculation logic to calculate a plurality of maximum operating voltage values each associated with a number of active cores of the plurality of cores, based at least in part on a plurality of coefficient values. In this way, the processor can operate at different maximum operating voltages dependent on the number of active cores. Other embodiments are described and claimed.

Calculating a dynamically changeable maximum operating voltage value for a processor based on a different polynomial equation using a set of coefficient values and a number of current active cores

Wear-out equalization techniques for multiple functional hardware units are disclosed. An integrated circuit includes a power control unit (PCU) configured to monitor indicators of wear-out incurred by multiple functional hardware units of the integrated circuit. The PCU calculates cumulative wear-out metrics of the functional hardware units based on the monitored indicators and performs an equalization action to equalize the cumulative wear-out metrics of the functional hardware units.

Wear-out equalization techniques for multiple functional units

Growing community of inventors

Palo Alto, CA, United States of America

Zhiguo Wang