Globalfoundries Inc.

Other

Globalfoundries U.S. Inc.

Zhiguo Sun

Huang Liu

Qiang Fang

Jiehui Shu

Hung-Wei Liu

Sipeng Gu

Haigou Huang

Jin Ping Liu

Sandeep Gaan

Jinping Liu

Keith Howard Tabakman

Ravi Prakash Srivastava

Suraj Kumar Patil

Shafaat Ahmed

Tsung-Liang Chen

Xinyuan Dou

Hui Zang

Guoxiang Ning

Joseph Francis Shepard, Jr

Sunil Kumar Singh

Huy Cao

Wei-Tsu Tseng

Christian Witt

Akshey Sehgal

Moosung M Chae

Yuping Ren

Daniel P Smith

Songkram Srivathanakul

Haifeng Sheng

Shishir K Ray

Wen-Pin Peng

Dinesh R Koli

Guoliang Zhu

Danni Chen

Adam Selsley

Xiaohan Wang

Changhong Wu

Daniel Fisher

Kumarapuram Gopalakrishnan

Yang Bum Lee

Cheng Xu

A semiconductor device is provided, which includes providing an active region, a source region, a drain region, a dielectric layer, a gate structure and a nitrogen-infused dielectric layer. The source region and the drain region are formed in the active region. The dielectric layer is disposed over the source region and the drain region. The gate structure formed in the dielectric layer is positioned between the source region and the drain region. The nitrogen-infused dielectric layer is disposed over the dielectric layer and over the gate structure.

Gate capping layers of semiconductor devices

A method of fabricating interconnects in a semiconductor device is provided, which includes forming an interconnect layer having a conductive line and depositing a first aluminum-containing layer over the interconnect layer. A dielectric layer is deposited over the first aluminum-containing layer, followed by a second aluminum-containing layer deposited over the dielectric layer. A via opening is formed in the second aluminum-containing layer through to the conductive line, wherein the via opening has chamferless sidewalls.

Chamferless interconnect vias of semiconductor devices

The present disclosure generally relates to semiconductor structures and, more particularly, to smooth sidewall structures and methods of manufacture. The method includes: forming a plurality of mandrel structures; forming a first spacer material on each of the plurality of mandrel structures; forming a second spacer material over the first spacer material; and removing the first spacer material and the plurality of mandrel structures to form a sidewall structure having a sidewall smoothness greater than the plurality of mandrel structures.

Method of forming smooth sidewall structures using spacer materials

Methods of self-aligned multiple patterning and structures formed by self-aligned multiple patterning. A mandrel line is patterned from a first mandrel layer disposed on a hardmask and a second mandrel layer disposed over the first mandrel layer. A first section of the second mandrel layer of the mandrel line is removed to expose a first section of the first mandrel layer. The first section of the first mandrel layer is masked, and the second sections of the second mandrel layer and the underlying second portions of the first mandrel layer are removed to expose first portions of the hardmask. The first portions of the hardmask are then removed with an etching process to form a trench in the hardmask. A second portion of the hardmask is masked by the first portion of the first mandrel layer during the etching process to form a cut in the trench.

Self-aligned multiple patterning processes with layered mandrels

The present disclosure relates to semiconductor structures and, more particularly, to a cobalt plated via integration scheme and methods of manufacture. The structure includes: a via structure composed of cobalt material; and a wiring structure above the via structure. The wiring structure is lined with a barrier liner and the cobalt material and filled with conductive material.

Cobalt plated via integration scheme

A method of forming hybrid Co and Cu CA/CB contacts and the resulting device are provided. Embodiments include forming a forming a plurality of trenches through an ILD down to a substrate; forming a first metal liner on side and bottom surfaces of each trench and over the ILD; annealing the first metal liner; forming a second metal liner over the first metal liner; forming a first plating layer over a portion of the second metal liner in each trench; forming a second plating layer over the second metal liner and first plating layer in a remaining portion of each trench, the first and second plating layers being different materials; and planarizing the second plating layer and the second and first metal liners down to the ILD.

Method to prevent cobalt recess

The present disclosure relates to semiconductor structures and, more particularly, to airgaps which isolate metal lines and methods of manufacture. The structure includes: a plurality of metal lines formed on an insulator layer; and a dielectric material completely filling a space having a first dimension between metal lines of the plurality of metal lines and providing a uniform airgap with a space having a second dimension between metal lines of the plurality of metal lines. The first dimension is larger than the second dimension.

Airgaps to isolate metallization features

One method disclosed herein includes performing a plurality of conformal deposition processes to form first, second and third layers of material within a contact opening, wherein the first layer comprises a contact insulating material, the second layer comprises a metal-containing material and the third layer comprises a conductive cap material, wherein the third layer is positioned above the second layer. The method further includes forming a contact ion implant region that is positioned at least partially in at least one of the first, second or third layers of material, forming a conductive material above the third layer and removing portions of the layers of material positioned outside of the contact opening.

Methods of forming MIS contact structures on transistor devices

One illustrative method disclosed herein includes, among other things, forming a plurality of trenches in a layer of insulating material, performing at least one damage-causing process operation to selectively damage portions of the insulating material adjacent the trenches, forming a conductive line in each of the trenches, after forming the conductive lines, performing a selective etching process to selectively remove at least portions of the damaged portions of the insulating material and thereby define an air gap positioned laterally adjacent each of the conductive lines, and forming a capping layer of material above the conductive lines, the air gap and the undamaged portion of the layer of insulating material.

Methods of forming air gaps in metallization layers on integrated circuit products

A starting metallization structure for electrically coupling one or more underlying semiconductor devices, the structure including a bottom layer of dielectric material with metal-filled via(s) situated therein, a protective layer over the bottom layer, and a top layer of dielectric material over the protective layer. A sacrificial layer of amorphous silicon is formed over the top layer of dielectric material, a protective layer is formed over the sacrificial layer and via(s) through each layer above the metal-filled via(s) to expose the metal of the metal-filled via(s). The protective layer is then selectively removed, as well as the sacrificial layer of amorphous silicon.

Sacrificial amorphous silicon hard mask for BEOL

Methods of lithographic patterning and structures formed by lithographic patterning. A hardmask layer is formed on a dielectric layer, a feature is formed on the hardmask layer, and a mandrel is formed that extends in a first direction across the first feature. The mandrel and the hardmask layer beneath the mandrel are removed to pattern the hardmask layer with the feature masking a section of the hardmask layer. After the hardmask layer is patterned, the dielectric layer is etched to form a first trench and a second trench that are separated by a section of the dielectric layer masked by the section of the hardmask layer. The first trench and the second trench are filled with a conductor layer to respectively form a first wire and a second wire that is separated from the first wire by the section of the dielectric layer.

Self-aligned lithographic patterning with variable spacings

A method that includes, among other things, forming first and second contact openings in a layer of insulating material that respectively expose a portion of first and second source/drain (S/D) regions of first and second transistors that are of the opposite type, forming first, second and third layers of material within each of the first and second contact openings, and forming an implant masking layer that masks the first contact opening while leaving the second contact opening exposed for further processing. The method also includes forming a contact ion implant region that is positioned at least partially in at least one of the first, second or third layers of material, removing the implant masking layer and forming a conductive material in both the first and second contact openings so as to define first and second MIS contact structures positioned in the first and second contact openings.

Methods of forming MIS contact structures on transistor devices in CMOS applications

Reducing liner corrosion during metallization of semiconductor devices at BEOL includes providing a starting metallization structure, the structure including a bottom layer of dielectric material with a via therein, a liner lining the via and extending over upper edges thereof, the lined via over filled with a conductive material, recessing the conductive material down to the liner, further selectively recessing the conductive material below the upper edges of the via without damaging the liner, and forming a cap of the liner material on the conductive material.

Reducing liner corrosion during metallization of semiconductor devices

Methods for fabricating a layered circuit structure are provided, which include, for instance: depositing a first material layer above a substrate, the first material layer having an oxidized upper surface; providing a second material layer over the oxidized upper surface of the first material layer; and inhibiting diffusion of one or more elements from the oxidized upper surface of the first material layer into either the first material layer or the second material layer during the providing of the second material layer over the oxidized upper surface of the first material layer. The inhibiting may include one or more of modifying a characteristic(s) of the first material layer, forming a protective layer over the oxidized upper surface of the first material layer, or altering at least one process parameter employed in providing the second material layer.

Inhibiting diffusion of elements between material layers of a layered circuit structure

A method for flowable oxide deposition is provided. An oxygen source gas is increased as a function of time or film depth to change the flowable oxide properties such that the deposited film is optimized for gap fill near a substrate surface where high aspect ratio shapes are present. The oxygen gas flow rate increases as the film depth increases, such that the deposited film is optimized for planarization quality at the upper regions of the deposited film.

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Halfmoon, NY, United States of America

Zhiguo Sun