Intel Corporation

Zhiguo Qian

Kemal Aygun

Jianyong Xie

Zhichao Zhang

Yu Zhang

Sanka Ganesan

Yu Amos Zhang

Shawna M Liff

Henning Braunisch

Mathew J Manusharow

Yidnekachew S Mekonnen

Johanna M Swan

Adel A Elsherbini

Robert L Sankman

Chia-Pin Chiu

Kaladhar Radhakrishnan

Gerald S Pasdast

Krishna Srinivasan

Zhaohui Zhu

Aleksandar Aleksov

Sujit Sharan

Brandon C Marin

Gang Duan

Dae-Woo Kim

Mayue Xie

Ajay Jain

Jieying Kong

Kemal Aygün

Feras Eid

Kristof Darmawikarta

Tao Wu

Kimin Jun

Zuoguo Wu

Leonel R Arana

Jeremy D Ecton

Jeff C Morriss

Jong-Ru Guo

Hongxia Feng

Mohammad Enamul Kabir

Jiwei Sun

Eduard Roytman

Tolga Memioglu

Cemil S Geyik

Peipei Wang

Gabriel Regalado Silva

Han Wui Then

Telesphor Kamgaing

Georgios C Dogiamis

Srinivas V Pietambaram

Ravindranath Vithal Mahajan

Saikumar Jayaraman

Edward Allyn Burton

Shigeki Tomishima

Sri Ranga Sai Boyapati

Wilfred Gomes

Kyu Oh Lee

Xiang Li

Ram S Viswanath

Krishna Bharath

Rajasekaran Swaminathan

Yikang Deng

Hongjiang Song

Tarek A Ibrahim

Andrew Paul Collins

Suddhasattwa Nad

Dingying David Xu

Sriram Srinivasan

Sri Chaitra Jyotsna Chavali

Richard J Dischler

Deepak Goyal

Gregorio R Murtagian

Xiaoying Guo

Daniel N Sobieski

Lakshmipriya Seshan

Kevin P O'brien

Marcel Arlan Wall

Matthew L Tingey

Daniel Krueger

Kevin Joseph Doran

Haobo Chen

Timothy A Gosselin

Prasanna Raghavan

Bohan Shan

Yan W Song

Prasad Ramanathan

Sarah Blythe

Simranjit S Khalsa

Hemachandar Tanukonda Devarajulu

Merve Celikkol

Yí Li

Hector Amador

Md Altai Hossain

Juan Zeng

Yiyang Zhou

Ahmad Siddiqui

Daryl Purcell

Jason Steill

Jackie C Preciado

Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

Ground via clustering for crosstalk mitigation

Glass substrates having signal shielding for use with semiconductor packages and related methods are disclosed. An example semiconductor package includes a core layer defining a channel and a through glass via (TGV). The channel at least partially surrounding the TGV. A signal transmission line is provided in the opening and extending through the core layer. An electrically conductive material positioned in the channel. The conductive material to provide electromagnetic shielding to the transmission line.

Glass substrates having signal shielding for use with semiconductor packages and related methods

Disclosed herein are capacitors and resistors at direct bonding interfaces in microelectronic assemblies, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component, wherein a direct bonding interface of the second microelectronic component is direct bonded to a direct bonding interface of the first microelectronic component, the microelectronic assembly includes a sensor, the sensor includes a first sensor plate and a second sensor plate, the first sensor plate is at the direct bonding interface of the first microelectronic component, and the second sensor plate is at the direct bonding interface of the second microelectronic component.

Capacitors and resistors at direct bonding interfaces in microelectronic assemblies

Processes and structures resulting therefrom for the improvement of high speed signaling integrity in electronic substrates of integrated circuit packages, which is achieved with the formation of airgap structures within dielectric material(s) between adjacent conductive routes that transmit/receive electrical signals, wherein the airgap structures decrease the capacitance and/or decrease the insertion losses in the dielectric material used to form the electronic substrates.

Airgap structures for high speed signal integrity

Embodiments disclosed herein include multi-die packages with interconnects between the dies. In an embodiment, an electronic package comprises a package substrate, and a first die over the package substrate. In an embodiment, the first die comprises a first IO bump map, where bumps of the first IO bump map have a first pitch. In an embodiment, the electronic package further comprises a second die over the package substrate. In an embodiment, the second die comprises a second IO bump map, where bumps of the second IO bump map have a second pitch that is different than the first pitch. In an embodiment, the electronic package further comprises interconnects between the first IO bump map and the second IO bump map.

Scalable and interoperable PHYLESS die-to-die IO solution

Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a first buildup layer and a second buildup layer over the first buildup layer. In an embodiment, a void is disposed through the second buildup layer. In an embodiment the electronic package further comprises a first pad over the second buildup layer. In an embodiment, the first pad covers the void.

Minimizing package impedance discontinuity through dielectric structure optimizations

Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

Microelectronic assemblies with inductors in direct bonding regions

An integrated circuit (IC) package, comprising a substrate that comprises a bridge die embedded within a dielectric. A first die comprising a first input/output (I/O) transmitter and a second die comprising a second I/O receiver and electrically coupled to the bridge die. A first signal trace and a first power conductor are within the bridge die. The first signal trace and the first power conductor are electrically coupled to the first I/O transmitter and the second I/O receiver. The first signal trace is to carry a digital signal and the first power conductor to provide a voltage for the second I/O receiver to read the digital signal.

Power-forwarding bridge for inter-chip data signal transfer

Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

Power delivery for embedded bridge die utilizing trench structures

An integrated circuit (IC) package substrate, comprising a metallization level within a dielectric material. The metallization level comprises a plurality of conductive features, each having a top surface and a sidewall surface. The top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness, and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness.

Selectively roughened copper architectures for low insertion loss conductive features

Embodiments include package substrates and a semiconductor package with such package substrates. A package substrate includes a first conductive layer in a first magnetic layer, and a second magnetic layer over the first magnetic layer, where the first and second magnetic layers include magnetic materials. The package substrate also includes a second conductive layer in the second magnetic layer. The second conductive layer includes a plurality of first traces fully surrounded by the first and second magnetic layers. The package substrate includes a third conductive layer over the second magnetic layer. The magnetic materials may include manganese Mn ferrite materials, Zn/Mn ferrite materials, or Ni/Zn ferrite materials. The magnetic materials include material properties with a low constant value, a magnetic tangent value, a frequency, a base filler chemistry, a filler shape, a filler orientation, a filler percentage, a loading fraction value, a permeability, an insertion loss, and a resin formulation.

Interconnect loss of high density package with magnetic material

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface, wherein the first die is embedded in a first dielectric layer, wherein the first surface of the first die is coupled to the second surface of the package substrate, and wherein the first dielectric layer is between a second dielectric layer and the second surface of the package substrate; a second die having a first surface and an opposing second surface, wherein the second die is embedded in the second dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the package substrate by a conductive pillar; and a shield structure that at least partially surrounds the conductive pillar.

Microelectronic assemblies

Generally discussed herein are systems, devices, and methods to reduce crosstalk interference. An interconnect structure can include a first metal layer, a second metal layer, a third metal layer, the first metal layer closer to the first and second dies than the second and third metal layers, the first metal layer including a ground plane within a footprint of a bump field of the interconnect structure and signal traces outside the footprint of the bump field.

Die interconnect structures having bump field and ground plane

An apparatus is provided which comprises: a substrate, the substrate comprising crystalline material, a first set of one or more contacts on a first substrate surface, a second set of one or more contacts on a second substrate surface, the second substrate surface opposite the first substrate surface, a first via through the substrate coupled with a first one of the first set of contacts and with a first one of the second set of contacts; a second via through the substrate coupled with a second one of the first set of contacts and with a second one of the second set of contacts, a trench in the substrate from the first substrate surface toward the second substrate surface, wherein the trench is apart from, and between, the first via and the second via, and dielectric material filling the trench. Other embodiments are also disclosed and claimed.

Dielectric-filled trench isolation of vias

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Chandler, AZ, United States of America

Zhiguo Qian