International Business Machines Corporation

Globalfoundries Inc.

Zhigang Song

Shidong Li

Oliver Desmond Patterson

Yunsheng Song

Junjun Li

Yongchun Xin

Hongqing Zhang

Guoda Lian

Junjing Bao

Jay A Bunt

Jang Sim

Qian Xu

William Davies, Jr

A flexible circuit substrate that includes a conductive line on a flexible substrate and at least one slot in the conductive line on the flex substrate, where at one slot is in an area of the flexible circuit substrate that will be bent to prevent an open in the conductive line on the flexible substrate.

Flexible circuit structure for circuit line bending

Tamper-respondent assemblies are provided which include a circuit board, an enclosure assembly mounted to the circuit board, and a pressure sensor. The circuit board includes an electronic component, and the enclosure assembly is coupled to the circuit board to enclose the electronic component within a secure volume. The enclosure assembly includes an enclosure with a sealed inner compartment, and a structural material within the sealed inner compartment of the enclosure. The structural material within the enclosure inhibits deflection of the enclosure due to a pressure differential between pressure of the sealed inner compartment and pressure around, at least in part, the enclosure. The pressure sensor senses pressure within the sealed inner compartment of the enclosure to facilitate identifying a pressure change indicative of a tamper event.

Tamper-respondent assembly with structural material within sealed inner compartment

Failure types that caused defective items to fail testing are identified, the defective items are grouped by the failure types to produce failure-type groups, and the defective items are analyzed to identify defect types that caused the failures. Failure-type limited yield within each of the failure-type groups, and failure-type group-specific defect ratio based on proportions of the defect types within each of the failure-type groups are determined. Additionally, each failure-type group-specific defect ratio is weighted using the failure-type limited yield to produce a weighted failure-type group-specific defect limited yield. For each of the defect types, the weighted failure-type group-specific defect limited yield from each of the failure-type groups is combined to produce the failure-type influenced defect-type total limited yield. Matrix processing is used for the weighting and combination processes. The defect types are ranked based on the failure-type influenced defect-type total limited yield.

Ranking defects with yield impacts

A method for depositing a conductor in the via opening electronic structure removes the via bottom liner so that the conductor deposited in the via opening directly contacts the underlying conductive layer. The method includes depositing amorphous silicon over the dielectric layer and the liner layer on the via opening sidewalls and bottom. The amorphous silicon extends substantially over the entire via opening while leaving below a void within the via opening. The amorphous silicon over the via opening and on the via opening bottom and the liner layer on the via opening bottom are anisotropically etched to leave a layer of amorphous silicon over the dielectric layer and the via opening side walls. The amorphous silicon is then removed to form a via opening having a substantially open-bottom liner. The conductor is then deposited in the via opening and contacts the underlying conductive layer.

Method for manufacturing in a semiconductor device a low resistance via without a bottom liner

A method for designing, a structure, method of inspecting and a computer system for designing voltage contrast integrated circuit characterization. The design method includes selecting a design level of a mask design shapes file; selecting a region of the design level having an open region having no design shapes and an adjacent circuit region having circuit design shapes; selecting a sub-region of the circuit region adjacent to the open region; copying design shapes of the sub-region to generate a characterization cell identical to the sub-region; modifying the characterization cell to generate a passive voltage contrast characterization cell; and placing the passive voltage contrast characterization cell into the open region adjacent to the sub-region to generate a modified design level.

Voltage contrast characterization structures and methods for within chip process variation characterization

A test structure of a semiconductor wafer includes a series of electrical units connected electrically in series output-to-input in an open loop configuration. The series of electrical units is configured to have alternating output voltages, such that each electrical unit is configured to output a voltage opposite an output voltage of a preceding electrical unit. Each electrical unit is configured to have an output voltage that alternates when an input voltage applied to a first electrical unit in the series of electrical units alternates.

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Hopewell Junction, NY, United States of America

Zhigang Song