International Business Machines Corporation

X Development LLC

University of Texas System

Zhigang Pan

Anthony Correale, Jr

Ruchir Puri

David Shing-Ki Kung

Raj B Apte

Cyrus Behroozi

Douglass T Lamb

Dino Ruic

Rajiv V Joshi

David Wallach

Minsik Cho

Owen Lewis

Peng Yu

Kathryn Heal

Systems, computer-implemented methods, and instructions encoded in machine-accessible storage media are provided for determining manufacturability of an integrated circuit layout. A computer-implemented method includes receiving a layout describing the integrated circuit to be manufactured by a semiconductor manufacturing process. The method also includes generating a differentiable manufacturability parameter as an output of a machine learning model using the layout, the machine learning model being trained to generate the differentiable manufacturability parameter. The differentiable manufacturability parameter describes the manufacturability of the integrated circuit by the semiconductor manufacturing process.

Differentiable model for manufacturability

A computer-implemented method for integrated circuit routing is described. The computer-implemented method comprising receiving a description of interconnected terminals of an integrated circuit with a wiring route electrically coupling the interconnected terminals and configuring a simulated environment defined via a plurality of voxels based on the description. The individual voxels included in the plurality of voxels each correspond to a spatial representation for a corresponding region of a layout associated with the integrated circuit. The computer-implemented method further includes determining local contributions of the individual voxels to a characteristic metric of the integrated circuit based on an electromagnetic simulation of the integrated circuit and revising the wiring route based on the local contributions of the individual voxels.

Voxel-based electromagnetic-aware integrated circuit routing

Embodiments of a system and method for generating integrated circuit layouts are described herein. A computer implemented method for generating integrated circuit layouts includes receiving a first layout for an integrated circuit, segmenting the first layout into a plurality of different patches, each patch of the plurality of patches describing a discrete portion of the first layout, identifying a non-compliant patch of the plurality of patches, the non-compliant patch violating a design rule governing the manufacture of the integrated circuit, generating a transformation of the non-compliant patch using a machine learning model, and generating a second layout using the transformation and the first layout, where the second layout is compliant with the design rule.

Machine learning based layout nudging for design rule compliance

A method for performing optical proximity correction with process variations considerations is disclosed. The maximum aerial gradient direction for a control point associated with an edge is initially determined. Then, a variational edge placement errorE&#x2009;along the maximum aerial image intensity gradient direction of the control point is calculated. A determination is made whether or not |CE&#xb7;n| is equal to or greater than a manufacturing grid, where n is the direction perpendicular to a segment pointing outward, and C is a constant. If |CE&#xb7;n| is equal to or greater than a manufacturing grid, the edge is moved by &#x2212;CE&#xb7;n.

Method and system for performing optical proximity correction with process variations considerations

A method for performing global routing on an integrated circuit design is disclosed. The integrated circuit design is initially divided into multiple G-cells. The G-cells are interconnected by a set of nets. The set of nets is then decomposed into corresponding wires. The wires are prerouted to interconnect the G-cells. BoxRouting is performed on the wires until all the wires are routed. Finally, postrouting is performed on the wires.

Method and system for performing global routing on an integrated circuit design

An integrated circuit (IC) design, method and program product for reducing IC design power consumption. The IC is organized in circuit rows. Circuit rows may include a low voltage island powered by a low voltage (V) supply and a high voltage island powered by a high voltage (V) supply. Circuit elements including cells, latches and macros are placed with high or low voltage islands to minimize IC power while maintaining overall performance. Level converters may be placed with high voltage circuit elements.

Multiple voltage integrated circuit and design method therefor

A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input signal from a lower voltage circuit. The first buffer drives a second buffer, which is supplied by a higher supply voltage. An output from the second buffer switches a supply select to selectively pass the higher supply voltage or a reduced supply voltage to the first buffer.

Single supply level converter

A method and program product for optimizing level converter placement in a multi supply integrated circuit. Each level converter is placed at a minimum power point to minimize net power and transitional delay from a first (low) voltage net source through the level converter and to a second (higher) voltage net sink. Then, inefficient level converters are eliminated. Level converters with fanin cones below a selected minimum cone size are deleted and low voltage sources to the deleted level converter reverted. Higher voltage level circuit elements receiving inputs from multiple level converters are replaced with equivalent low voltage circuit elements. Low voltage buffer driving level converters are both replaced by a single said level converter.

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Austin, TX, United States of America

Zhigang Pan