Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.

Other

Zhida Xu

Ilgon Kim

Xiaohui Yao

Jun Zhao

Xin Hui Zhang

Bin Zhao

Hua Fu

Shanglong Wang

A display device is provided, including a circuit board, a display panel, a plurality of clock signal lines, and a plurality of grounding resistors. Each clock signal line extends from the circuit board to a non-display area of the display panel. The plurality of grounding resistors are disposed on the circuit board. Each grounding resistor is connected to a corresponding clock signal line, and is configured to reduce a voltage value of high level of the clock signal.

Display device

A array substrate includes a plurality of stages of cascaded GOA units and a plurality of corresponding clock signal lines electrically connected to them. Each stage of GOA units includes a first output transistor. In the plurality of stages of GOA units, the plurality of first output transistors increase in size along a predetermined direction. The predetermined direction is a signal transmission direction of any of the clock signal lines.

Array substrate including stages of gate array units having different sized output transistors, and display panel

The present application provides an array substrate and a display panel. The array substrate includes fan-out regions and an inverted region formed between two adjacent fan-out regions. The array substrate includes metal lines and floating metal lines. The metal lines include first metal lines in the fan-out region and second metal lines in the inverted triangle region. The floating metal lines include a first floating metal line arranged between the first metal lines and the second metal lines. The array substrate includes an alignment film arranged on the metal lines and the floating metal lines.

Array substrate and display panel

The present application provides a GOA device and a gate driving circuit. The GOA device includes a pull-up control circuit, a bootstrap capacitor, a pull-up circuit, a pull-down circuit, and a pull-down holding circuit. The present application decreases a number of TFTs of the gate driving circuit and simplifies a structure of the gate driving circuit by multiplexing the bootstrap capacitor, the pull-down circuit, and the pull-down holding circuit.

GOA device and gate driving circuit

A driving circuit and a display panel are provided. In a driving circuit structure, a clock signal line group includes a plurality of clock signal lines, the clock signal lines are arranged side by side, and there is a first pitch between two adjacent clock signal lines. A non-high frequency signal line is provided on two sides of the clock signal line group. A redundant clock signal line is disposed between the clock signal line group and the non-high frequency signal line, and a frequency and an amplitude of a signal received by the redundant clock signal line are the same as a frequency and an amplitude of a signal received by the clock signal line.

Driving circuit comprising redundant clock signal line and display panel

A display driving circuit and a display device are proposed. The display driving circuit includes a plurality of driving sets. Each of the plurality of driving sets is electrically connected to all scan lines of the display device. The scan lines are electrically connected to a display unit of the display device. Each of the plurality of driving sets controls a display function of the display device through the scan lines. Each of the plurality of driving sets is electrically connected to a triggering signal line, the triggering signal line is configured to control the plurality of driving sets to drive the display device in turn.

Display driving circuit and display device

The present disclosure provides a GOA device and a gate drive circuit. The GOA device includes at least two GOA units in cascade. The present disclosure connects the input terminal of the pull-up control circuit to the start signal of the n&#x2212;7-th stage, the control node (Qn) of the n-th GOA unit is thus pulled up to the first high potential and the bootstrap capacitor is charged. The control node (Qn) is charged 7 stages in advance, which resolves the technical problem of insufficient charging of the high-resolution high-refresh rate display panel in the related art.

Growing community of inventors

Guangdong, China

Zhida Xu