Intel Corporation

Zhichao Zhang

Kemal Aygun

William J Lambert

Zhiguo Qian

Tao Wu

Srikant Nekkanty

Yidnekachew S Mekonnen

Jiwei Sun

Robert L Sankman

Sanka Ganesan

Adel A Elsherbini

Kai Xiao

Sri Chaitra Jyotsna Chavali

Gaurav Chawla

Zhenguo Jiang

Tolga Memioglu

Aleksandar Aleksov

Feras Eid

Henning Braunisch

Mathew J Manusharow

Pooya Tadayon

Krishna Bharath

Joshua Heppner

Sidharth Dalmia

Kuang C Liu

Gregorio R Murtagian

Gong Ouyang

Javier Soto

Omkar G Karhade

Eric Jin Li

Xiang Li

Michael J Hill

Jimin Yao

David J Llapitan

Trang Thuy Thai

Zhe Chen

Stephen Andrew Smith

Sujit Sharan

Shawna M Liff

Kyu Oh Lee

Cheng Xu

Rajasekaran Swaminathan

Yikang Deng

Donald Tiendung Tran

Andrew James Brown

Jianyong Xie

Ji Yong Park

Xiaoqian Li

Changhua Liu

Steven A Klein

Vijaykumar Krithivasan

Liang Zhang

Feifei Cheng

Liwei Cheng

Jeffrey Lee

Stephen Smith

Debendra Mallik

James A McCall

George Vergis

Zuoguo Wu

Fay Hua

Ram S Viswanath

Brandon C Marin

Zhen Zhou

Mitul Bharat Modi

Hongjiang Song

Jeffory L Smalley

Tarek A Ibrahim

Joe F Walczyk

Sriram Srinivasan

Dimitrios Ziakas

Bassam N Coury

Beom-Taek Lee

Mayue Xie

Sri Chaitra J Chavali

Mohiuddin M Mazumder

Chong J Zhao

Jun Liao

Jong-Ru Guo

Jonathan W Thibado

Mani Prakash

John M Lynch

Feroz Mohammad

Michael Garcia

Daqiao Du

Cemil S Geyik

Suresh V Pothukuchi

Kemal Aygün

Michael E Ryan

Sri Chaitra Chavali

Yan W Song

Thomas T Holden

Ahmet C Durgun

Khine N Han

Li Sun

Guneet Kaur

Srichaitra Chavali

A microelectronic socket structure and a method of forming the same. The socket structure comprises: a socket structure housing defining a cavity therein; and an interconnection structure including: a contact element disposed at least in part within the cavity, and configured to be electrically coupled to a corresponding microelectronic package, the contact element corresponding to one of a signal contact element or a ground contact element; and a conductive structure disposed at least in part within the cavity, electrically coupled to the contact element, and having an outer contour that is non-conformal with respect to an outer contour of the contact element.

Heterogenous socket contact for electrical and mechanical performance scaling in a microelectronic package

Integrated circuit packages may be formed having at least one optical via extending from a first surface of a package substrate to an opposing second surface of the package substrate. The at least one optical via creates an optical link between the opposing surfaces of the package substrate that enables the fabrication of a dual-sided optical multiple chip package, wherein integrated circuit devices can be attached to both surfaces of the package substrate for increased package density.

Through-substrate optical vias

Techniques and mechanisms for facilitating horizontal communication with a photonic integrated circuit (PIC) chip, and a lens structure which is optically coupled thereto. In an embodiment, a PIC chip comprises integrated circuitry, photonic waveguides, and integrated edge-oriented couplers (IECs) which are coupled to the integrated circuitry via the photonic waveguides. The PIC chip forms respective first divergent lens surfaces of the IECs, which are each at a respective terminus of a corresponding one of the photonic waveguides. A lens structure, which is adjacent to the IECs, comprises a second divergent lens surface having an orientation which is substantially orthogonal to the respective orientations of the first divergent lens surfaces. In another embodiment, an edge of the PIC chip forms one or more recess structures, and the lens structure comprises one or more tenon portions which each extends into a respective recess structure of the one or more recess structures.

Device, method and system for optical communication with a photonic integrated circuit chip and a transverse oriented lens structure

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a core substrate with a first conductive structure having a first thickness on the core substrate, and a second conductive structure having a second thickness on the core substrate, where the first thickness is different than the second thickness.

Microelectronic assemblies having conductive structures with different thicknesses on a core substrate

Techniques and mechanisms for optically coupling a photonic integrated circuit (PIC) chip to an optical fiber via a planar optical waveguide structure. In an embodiment, a PIC chip comprises integrated circuitry, photonic waveguides, and integrated edge-oriented couplers (IECs) which are coupled to the integrated circuitry via the photonic waveguides. The PIC chip forms respective divergent lens surfaces of the IECs, which are each at a respective terminus of a corresponding one of the photonic waveguides. A planar optical waveguide structure, which is adjacent to the IECs, comprises a core which is optically coupled between the PIC chip and an array of optical fibers. In another embodiment, an edge of the PIC forms a stepped structure, wherein an upper portion of the stepped structure comprises the plurality of coplanar IECs, and a lower portion of the stepped structure extends past the plurality of coplanar IECs.

Device, method and system for optical communication with a waveguide structure and an integrated optical coupler of a photonic integrated circuit chip

Embodiments described herein may be related to apparatuses, processes, and techniques related to disaggregating co-packaged SOC and photonic integrated circuits on an multichip package. The photonic integrated circuits may also be silicon photonics engines. In embodiments, multiple SOCs and photonic integrated circuits may be electrically coupled, respectively, into modules, with multiple modules then incorporated into an MCP using a stacked die structure. Other embodiments may be described and/or claimed.

Optical multichip package with multiple system-on-chip dies

In an embodiment, a socket comprises a housing, where the housing is a dielectric material. In an embodiment, a shell passes through a thickness of the, where the shell is conductive. The socket may further comprise a plug within the shell, where the plug is a dielectric material, and where the plug has a bottom surface. In an embodiment, a pin passes through the thickness of the housing within an inner diameter of the shell, where the pin has a first portion with a first diameter and a second portion with a second diameter, and where the pin is conductive. In an embodiment, the socket further comprises a spring around the first portion of the pin, where a first end of the spring presses against the bottom surface, and where a second end of the spring presses against the second portion of the pin.

Coaxial transmission line SLI socket designs for 224GBS and beyond

Techniques and mechanisms for coupling packaged devices with a socket device. In an embodiment, the socket device comprises a socket body structure and conductors extending therethrough. A pitch of the conductors is in a range of between 0.1 millimeters (mm) and 3 mm. First and second metallization structures also extend, respectively, from opposite respective sides of the socket body structure. In the socket body structure, a conductive shield structure, electrically coupled to the first and second metallization structures, substantially extends around one of the conductors. For each of the first and second metallization structures, a vertical span of the metallization structure is in a range of between 0.05 mm and 2.0 mm, a portion of a side of the metallization structure forms a respective corrugation structure, and a horizontal span of the portion is at least 5% of the vertical span of the metallization structure.

Dual-sided socket device with corrugation structures and shield structures

An RF chip package comprises a housing and one or more conductive contacts designed to electrically connect the RF chip package to other conductive contacts. The housing includes a first substrate, a 3-D antenna on the first substrate, and a second substrate. The second substrate includes a plurality of semiconductor devices and is bonded to the first substrate. An interconnect structure allows for electrical connection between the first and second substrates. In some cases, the first substrate is flip-chip bonded to the second substrate or is otherwise connected to the second substrate by an array of solder balls. By integrating both the 3-D antenna and RF circuitry together in the same chip package, costs are minimized while bandwidth is greatly improved compared to a separately machined 3-D antenna.

In-package 3D antenna

Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure on a low density interconnect (LDI) printed circuit board (PCB) according to an LDI fabrication process and forming one or more fine conductive features on the LDI PCB by performing a fine feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fine gap region within the conductive structure. Other embodiments are described and claimed.

Fine feature formation techniques for printed circuit boards

In accordance with disclosed embodiments, there is an antenna package using a ball attach array to connect an antenna and base substrates of the package. One example is an RF module package including an RF antenna package having a stack material in between a top and a bottom antenna layer to form multiple antenna plane surfaces, a base package having alternating patterned conductive and dielectric layers to form routing through the base package, and a bond between a bottom surface of the antenna package and to a top surface of the base package.

Antenna package using ball attach array to connect antenna and base substrates

Embodiments include assemblies. An assembly includes a substrate having a first interconnect and a second interconnect. The first interconnect has a first conductive pad and a second conductive pad, and the second interconnect has a third conductive pad and a fourth conductive pad. The assembly includes a socket over the substrate. The socket has a first pin, a second pin, and a base layer with a first pad and a second pad. The first and second pins are vertically over the respective first and second interconnects. The first pad is directly coupled to the first pin and fourth conductive pad, while the second pad is directly coupled to the second pin and second conductive pad. The first pad is positioned partially within a footprint of the third conductive pad, and the second pad is positioned partially within a footprint of the first conductive pad.

Differential crosstalk self-cancelation in stackable structures

Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.

Integrated circuit structures in package substrates

Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.

Low loss and low cross talk transmission lines with stacked dielectric layers for forming stubs of different thickness or for forming a coaxial line

Embodiments include a transmission line-land grid array (TL-LGA) socket assembly, a TL-LGA socket, and a package substrate. The TL-LGA socket assembly includes a TL-LGA socket having an interconnect in a housing body, the interconnect includes a vertical portion and a horizontal portion. The housing body has a top surface and a bottom surface, where the top surface is a conductive layer. The TL-LGA socket assembly also includes a package substrate having a base layer having a signal pad and a ground strip. The base layer is above the conductive layer of the housing body of the TL-LGA socket. The ground strip is above the horizontal portion of the interconnect and adjacent to the signal pad. The horizontal portion is coupled to the signal pad on the base layer. The package substrate may have a pad with a reduced pad area.

Selective ground flood around reduced land pad on package base layer to enable high speed land grid array (LGA) socket

Growing community of inventors

Chandler, AZ, United States of America

Zhichao Zhang