Synaptics Corporation

Zhibing Liu

Stephen L Morein

Prashant Shamarao

Jay Liang

In one embodiment, a system includes one or more source drivers operable to drive a portion of a row or column of a display. The system also includes a timing controller coupled to each of the one or more source drivers and configured to control the one or more source drivers. The system further includes a downstream link for each of the one or more source drivers, configured to transfer data from the timing controller to one of the one or more source drivers. The system also includes an upstream link for each of the one or more source drivers, configured to transfer uplink data from one of the one or more source drivers to the timing controller, wherein the uplink data includes at least one of downlink lock status information and touch data.

Source driver uplink as indicator of downlink status

A digital video communication device is provided. The digital video communication device includes a transmitter providing a spread-spectrum video signal including a predetermined frequency spread value and a frequency ratio and a receiver receiving the spread-spectrum video signal. The receiver includes a frequency synthesizer, a free-running clock generator configured to generate a free-running clock signal, wherein the free-running clock signal is used as a reference clock signal input to the frequency synthesizer. The receiver further includes a digital control logic circuit configured to separate the frequency ratio from the spread-spectrum video signal, and a line buffer coupled to the digital control logic circuit and the frequency synthesizer, the line buffer adjusting the frequency ratio and sending the adjusted frequency ratio to the frequency synthesizer, wherein the frequency synthesizer combines the free-running clock signal and the adjusted frequency ratio, and outputs a de-spread clock signal.

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San Jose, CA, United States of America

Zhibing Liu