Applied Materials, Inc.

Apple Inc.

Zhibin Wang

Byungkook Kong

Sang Wook Kim

Sang-jun Choi

Chang Wook Doh

John Stephen Smith

Blake R Marshall

Vipin Ayanoor-Vitikkate

Daniel Jacob Benjamin Bechstein

Robert Ubo Liu

MohammadAli Khorrami

Kyoungjin Lee

Ying Cao

An electrostatic discharge (ESD) robust design for an input device such as a stylus is disclosed. The input device can include one or more components, such as one or more Schottky diodes, that can be damaged by ESD events. To reduce the likelihood of damage to sensitive components, the parasitic capacitance between sensitive conductive paths and reference ground paths of the input device that could otherwise provide electrostatic discharge paths can be reduced (arranging current limiting resistance at specific locations among sensitive components, creating physical separation between sensitive conductive paths and reference ground paths), shielding can be added to shield the sensitive electronics from ESD pulses, and high dielectric breakdown material can be added to prevent ESD pulse entry or exit of not otherwise protected circuit parts.

Electrostatic discharge robust design for input device

Embodiments of the present disclosure generally provide a method and apparatus for forming features in a material layer utilizing EUV technologies. In one embodiment, a method of patterning a substrate includes disposing a patterned photoresist layer on a mask layer disposed on a substrate, wherein the patterned photoresist layer has openings with different widths defined in the patterned photoresist layer, forming a compensatory layer along sidewalls of the patterned photoresist layer to modify the widths of the openings and etching the mask layer through the openings with the modified width.

Uniform EUV photoresist patterning utilizing pulsed plasma process

Systems and methods discussed herein are directed towards processing of substrates, including forming a plurality of features in a target layer on a substrate. The formation of the plurality of features includes a main etch operation that forms the plurality of features to a first depth in the target layer. The main etch operation is followed by a phase shift sync pulsing (PSSP) operation, and these two operations are repeated iteratively to form the features to a predetermined depth. The PSSP operation includes one or more cycles of RF source power and RF bias power, this cycle deposits a protective coating in and on the features and then etches a portion of the protective coating to expose portions of the feature.

Device fabrication via pulsed plasma

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San Jose, CA, United States of America

Zhibin Wang