United Microelectronics Corp.

Globalfoundries Singapore Pte. Ltd.

United Microelectorincs Corp.

Zhibiao Zhou

Chi-Fa Ku

Shao-Hui Wu

Chen-Bin Lin

Ding-Lung Chen

Xing Hua Zhang

Chun-Yuan Wu

Chung-Yuan Lee

Yuanli Ding

Chia-Fu Hsu

Sanpo Wang

Yu-Cheng Tung

Purakh Raj Verma

Su Xing

Chen-Hsien Hsu

Wei-Jen Wang

Li Wang

Yudi Setiawan

Chien-Fu Chen

Ching-Yang Wen

Chi-Chang Shuai

Hai Biao Yao

Qinggang Xing

Runshun Wang

Pengfei Guo

Xu Yang Shen

Bo Tao

Shan Liu

Dong Yin

Jian Xie

Gang Ren

A high electron mobility transistor (HEMT) includes a first doped layer disposed in a substrate, a mesa isolation disposed on the substrate, a gate electrode disposed on the mesa isolation, a source electrode and a drain electrode disposed adjacent to two sides of the gate electrode, a passivation layer disposed on the mesa isolation and around the source electrode and the drain electrode, a first metal line connecting the source electrode and the first doped layer, and a second metal line connecting the drain electrode and the first doped layer.

High electron mobility transistor

A method of manufacturing a layout structure of Micro LED for augmented reality and mixed reality is provided in the present invention, including steps of providing a substrate with multiple display units arranged thereon to form an unit array and includes an edge region and a transparent region surrounded by the edge region, forming pixel driver circuits and a first transparent layer on the edge region, setting multiple Micro LEDs on the first transparent layer of edge regions, forming a second transparent layer on the Micro LEDs and the first transparent layer, thinning and removing the substrate on the transparent region to expose the first transparent layer, and forming a protection layer on back sides of the substrate and the exposed first transparent layer.

Micro LED layout for augmented reality and mixed reality and method of manufacturing the same

A semiconductor structure includes a semiconductor on insulator (SOI) substrate, a first electrically conductive structure, and a second electrically conductive structure. The SOI substrate includes a base substrate, a buried insulation layer disposed on the base substrate, a semiconductor layer disposed on the buried insulation layer, and a trap rich layer disposed between the buried insulation layer and the base substrate. At least a part of the first electrically conductive structure and at least a part of the second electrically conductive structure are disposed in the trap rich layer. A part of the trap rich layer is disposed between the first electrically conductive structure and the second electrically conductive structure. The first electrically conductive structure, the second electrically conductive structure, and the trap rich layer disposed between the first electrically conductive structure and the second electrically conductive structure are at least a portion of an anti-fuse structure.

Semiconductor structure

A layout of Micro LED for augmented reality (AR) and mixed reality (MR) is provided in the present invention, including multiple display cells arranging into a cell array, multiple micro LEDs set on the edge region of each display cell and exposing the transparent region surrounded by the edge region, and pixel driver circuits set on the edge region right under the Micro LEDs.

An oxide semiconductor device and a method for manufacturing the same are provided in the present invention. The oxide semiconductor device includes a back gate, an oxide semiconductor film, a pair of source and drain electrodes, a gate insulating film, a gate electrode on the oxide semiconductor film with the gate insulating film therebetween, an insulating layer covering only over the gate electrode and the pair of source and drain electrodes, and a top blocking film over the insulating layer.

Oxide semiconductor device and method of manufacturing the same

A semiconductor structure is provided, the semiconductor structure includes a front oxide layer on a backside oxide layer, a front electronic component in the front oxide layer, a backside electronic component in the backside oxide layer, and a shield structure disposed between the front oxide layer and the backside oxide layer, the shield structure includes a patterned buried metal layer, two front contact structures disposed on a front surface of the patterned buried metal layer, and two back contact structures disposed on a backside of the patterned buried metal layer.

Semiconductor structure and method for forming the same

The present invention provides a layout of a semiconductor transistor device including a first and a second active area, a first and a second gate, and a metal line. The first active and the second active area are extended along a first direction. The first gate and the second gate are extended along a second direction and crossed the first active area, to define two transistors. The two transistors are electrically connected with each other through a conductive layer. The metal line is disposed on the conductive layer and is electrically connected the two transistors respectively.

Layout of semiconductor transistor device

The present invention provides a method for forming a semiconductor structure, the method includes: firstly, a substrate having a recess disposed therein is provided, wherein the substrate comprises a silicon substrate, next, a first element is formed in the recess and arranged along a first direction, wherein the first element is made of an oxidation semiconductor material, afterwards, a dielectric layer is formed on the first element, and a second element is formed on dielectric layer and arranged along the first direction, wherein the second element is used as the gate structure of a transistor structure.

Method for forming semiconductor structure

A semiconductor device includes a substrate, a source region and a drain region, a gate dielectric layer, and a ferroelectric material layer. The ferroelectric material layer overlaps with the source region and overlaps with the drain region. The substrate further comprises a channel layer. A gate electrode is disposed on the substrate. The ferroelectric material layer is disposed between the channel layer and the gate electrode.

Semiconductor device having a ferroelectric material layer

A semiconductor device includes a substrate, a semiconductor channel layer, a gate electrode, and a first memory structure. The semiconductor channel layer is disposed on the substrate. The gate electrode and the first memory structure are disposed on the semiconductor channel layer. The first memory structure includes a first bottom plate, a first top plate, and a first memory element layer. The first top plate is disposed on the first bottom plate. The first memory element layer is disposed between the first bottom plate and the first top plate. The first bottom plate contacts the semiconductor channel layer. Purposes of process simplification and/or memory density enhancement may be achieved by integrating a transistor with a memory structure.

Semiconductor device and manufacturing method thereof

A dual mode memory system is provided in the present invention, which includes a memory cell array with a plurality of oxide-semiconductor field effect transistors, each said oxide-semiconductor field effect transistor has a ferroelectric layer in the bottom gate to modulate the bottom gate bias voltage according to the polarization voltages provided by the dual mode control unit.

Dual mode memory system and method of working the same

An image sensor includes a first pixel and a second pixel. The first pixel receives a first signal sensed by a first photodiode. The second pixel receives a second signal sensed by a second photodiode. A pixel binning device includes a first transistor, a second transistor and a binning circuit, wherein the first transistor switchably couples to the first pixel to transfer the first signal, the second transistor switchably couples to the second pixel to transfer the second signal, and the binning circuit couples to the first transistor and the second transistor to bin the first signal and the second signal.

Image sensor with pixel binning device

A 6T SRAM cell includes a substrate having thereon a first pull-up (PU-) transistor, a first pull-down (PD-) transistor, a second pull-up (PU-) transistor, and a second pull-down (PD-) transistor. A first contact hard mask partially overlaps with a source diffusion region of the PU-transistor. A second contact hard mask partially overlaps with a first gate and a source diffusion region of the PD-transistor. A first contact plug partially lands on the first contact hard mask and partially lands on the source diffusion region of the PU-transistor. A second contact plug partially lands on the second contact hard mask and partially lands on the source diffusion region of the PD-transistor.

Growing community of inventors

Singapore, Singapore

Zhibiao Zhou