Qualcomm Incorporated

Zhi Zhu

Xiaohua Kong

Miao Li

Li Hsiang Sun

Nam Dang

Lew G Chua-Eoan

Zhiqin Chen

Junmou Zhang

Yu Song

Tirdad Sowlati

Ying Duan

Nir Gerber

Deqiang Song

Jason R Gonzalez

Jing Wu

Jon Boyette

Jie Xu

Russell Deans

Yuancheng Christopher Pan

Vannam Dang

Fifin Sweeney

Christian Josef Wiesner

Xiaochun Zhu

Sei Seung Yoon

Jingcheng Zhuang

Minhan Chen

Cheng Zhong

Chad Everett Winemiller

Bupesh Pandita

Madjid Hafizi

Eskinder Hailu

Kenneth Arcudia

Hao Liu

Dong Ren

Hadi Goudarzi

Ohjoon Kwon

Hongmei Liao

Chia Heng Chang

William Knox Ladd

Lejie Lu

Behnam Amelifard

Yan Hu

Nam V Dang

Yuan-cheng Christopher Pan

Mark Wesley Vilas

Kevin Wayne Spears

Minghsien Tsai

Younwoong Chung

Yong Suk Jun

Jason Gonzalez

Jon Raymond Boyette

Russell Coleman Deans

A receiver has a first equalizer circuit that includes a first stage having a source degeneration circuit and a trans-impedance amplifier (TIA). The source degeneration circuit includes a resistor coupled in parallel with a capacitor. The TIA includes an embedded variable gain amplifier with a gain controlled by feedback resistors. Each feedback resistor is coupled between input and output of the TIA. In some implementations, the receiving circuit has a second equalizer circuit coupled in series with the first equalizer circuit. The second equalizer circuit includes a first stage having a source degeneration circuit and a TIA. The source degeneration circuit in the second equalizer circuit has a source degeneration resistor coupled in parallel with a source degeneration capacitor and the TIA includes an embedded variable gain amplifier whose gain is controlled by feedback resistors coupled between input and output of the TIA in the second equalizer circuit.

Analog receiver front-end with variable gain amplifier embedded in an equalizer structure

An equalizing circuit includes a first current summer that receives a data signal and a first plurality of feedback signals, a first multiplexer that selects a first sampling clock signal from a plurality of clock signals using a signal that indicates a mode of operation of the equalizing circuit, and a first slicer that samples the output of the first current summer in accordance with timing provided by the first sampling clock signal. The equalizing circuit can have a second current summer that receives the data signal and a second plurality of feedback signals, a second multiplexer that selects a second sampling clock signal from the plurality of clock signals using the signal that indicates the mode of operation of the equalizing circuit, and a second slicer that samples the output of the second current summer according to timing provided by the second sampling clock signal.

Multi-mode non-loop unrolled decision-feedback equalizer with flexible clock configuration

A receiver including a first differential sense amplifier configured to amplify an input differential data signal to generate an output differential data signal; a first set of one or more differential decision feedback equalizer (DFE) taps configured to modify the output differential data signal based on a set of one or more differential tap signals, wherein the first set of one or more differential DFE taps affect an output common mode voltage associated with the output differential data signal; and a compensation circuit configured to adjusts the output common mode voltage to compensate for the effect on the output common mode voltage by the set of one or more differential DFE taps. The compensation circuit includes reference and replica receivers to generate reference and replica output common mode voltages, and a feedback circuit to adjust the output common mode voltage based on the reference and replica output common mode voltages.

Compensation of common mode voltage drop of sensing amplifier output due to decision feedback equalizer (DFE) taps

A receiver is provided that includes a time-to-digital converter for converting a phase difference between a clock signal and a received data signal into a phase-difference digital code. The receiver also includes a logic circuit that controls a programmable delay line to delay the clock signal into a delayed clock signal by a delay that is responsive to a difference between the phase-difference code and a unit interval for the clock signal. The delayed clock signal clocks a flip-flop to register the received data signal.

Low-power, low-latency time-to-digital-converter-based serial link

Certain aspects of the present disclosure generally relate to techniques and apparatus for doubling the frequency of a signal. For example, certain aspects are directed to a phase frequency detector (PFD)-based rising-edge-delay-only frequency doubling circuit. One example frequency doubler circuit generally includes a first delay stage, a second delay stage, a first PFD, a first rising-edge-only adjustable delay cell, a second PFD, a second rising-edge-only adjustable delay cell a logic gate, and a comparator configured to compare a direct-current (DC) voltage value of an output of the logic gate with a reference voltage and control the first and second rising-edge-only adjustable delay cells based on the comparison.

Frequency doubler based on phase frequency detectors using rising edge delay

An apparatus and methods are disclosed for a bidirectional front-end circuit included within a system on chip (SoC). The bidirectional front-end circuit includes a differential bidirectional terminal for receiving and transmitting signals. The bidirectional front-end circuit is configured to provide a first communication path between a first controller and a connector through the differential bidirectional terminal when operating in a first mode. And, the bidirectional front-end circuit is reconfigured to provide a second communication path between a second controller and the connector through the differential bidirectional terminal when operating in a second mode.

Apparatus and methods for providing a reconfigurable bidirectional front-end interface

In certain aspects, an apparatus includes a multiplexer having a first input, a second input, a select input, and an output, wherein the first input is configured to receive a first reference clock signal, the second input is configured to receive a second reference clock signal, and the select input is configured to receive a select signal. The multiplexer is configured to select one of the first and second reference clock signals based on the select signal, and output the selected one of the first and second reference clock signals at the output of the multiplexer. The apparatus also includes a clock driver having an input and an output, wherein the input of the clock driver is coupled to the output of the multiplexer.

Efficient clock forwarding scheme

Systems and methods for adjusting a phase step size of a clock data recover (CDR) circuit are described according to aspects of the present disclosure. In certain aspects, a method for adjusting a phase step size of a CDR circuit includes sensing a frequency offset of the CDR circuit, and adjusting the phase step size of the CDR circuit based on the sensed frequency offset. The frequency offset may be sensed by sensing a signal level on an integration path of a loop filter of the CDR circuit. The phase step size of the CDR circuit may be adjusted by switching the CDR circuit between a first phase step size and a second phase step size using a modulator (e.g., a sigma-delta modulator).

Clock data recovery with non-uniform clock tracking

An on-chip passive transmission channel is provided for the propagation of serialized data from a first controller to a dual-protocol physical layer interface. A second controller for the dual-protocol physical layer interface is located closer on a semiconductor die to the dual-protocol physical layer interface than the first controller.

Controller-PHY connection using intra-chip SerDes

Aspects disclosed in the detailed description include communicating low-speed and high-speed parallel bit streams over a high-speed serial bus. In one aspect, a data transmitting circuit converts a low-speed parallel bit stream into a high-speed parallel bit stream and then serializes the converted high-speed parallel bit stream based on a high-speed reference frequency. In another aspect, a data receiving circuit recovers the low-speed parallel bit stream from the high-speed parallel bit stream if the low-speed parallel bit stream is determined to exist in the high-speed parallel bit stream. By serializing and deserializing the low-speed parallel bit stream based on the high-speed reference frequency, it is possible to communicate the high-speed parallel bit stream and the low-speed parallel bit stream over the high-speed serial bus without requiring additional serializers and deserializers, thus reducing component costs and implementation complexities in both the transmitting circuit and the receiving circuit.

Communication low-speed and high-speed parallel bit streams over a high-speed serial bus

Power saving systems and methods for Universal Serial Bus (USB) systems are disclosed. When a USB physical layer (PHY) enters a U3 low power state, not only are normal elements powered down, but also circuitry within the USB PHY associated with detection of a low frequency periodic signal (LFPS) wake up signal is powered down. A low speed reference clock signal is still received by the USB PHY, and a medium speed clock within the USB PHY is activated once per period of the low speed reference clock signal. The medium speed clock activates the signal detection circuitry and samples a line for the LFPS. If no LFPS is detected, the signal detection circuitry and the medium speed clock return to low power until the next period of the low speed reference clock signal. If the LFPS is detected, the USB PHY returns to a U0 active power state.

Power saving systems and methods for Universal Serial Bus (USB) systems

In one embodiment, a receiver comprises a latch configured to receive a data signal and to latch symbols of the received data signal, and a decision feedback equalizer. The decision feedback equalizer comprises a first feedback capacitor having first and second terminals, the first terminal being coupled to a first internal node of the latch. The decision feedback equalizer also comprises a first plurality of switches configured to alternatively couple the second terminal of the first feedback capacitor to a first feedback signal and a ground, the first feedback signal having a first voltage that is a function of a bit decision corresponding to a first previous symbol in the data signal preceding a current symbol in the data signal.

Switch capacitor decision feedback equalizer with internal charge summation

A phase interpolator, including: a first portion including a first plurality of branches and a plurality of tail current sources, each branch including a differential pair of transistors, source terminals of the differential pair of transistors connect to form a source node, wherein each tail current source couples to one of the source nodes, and wherein the differential pair of transistors and the corresponding tail current source are configured in a current coding scheme; a second portion including a second plurality of branches and a fixed current source coupled to the second plurality of branches, each branch of the second plurality of branches including a second plurality of differential pairs of transistors and a plurality of switches configured in a size coding scheme; wherein the first portion and the second portion are coupled to each other and to a pair of load resistors.

Linearity of phase interpolators by combining current coding and size coding

A clock and data recovery (CDR) circuit produces an in-phase clock, a quadrature clock offset by 90 degrees from the in-phase clock, and an auxiliary clock offset from the in-phase clock by a fraction of 90 degrees. A data sampler cyclically samples a data signal to form sets of samples according to the in-phase, quadrature, and auxiliary clocks, each set comprising an in-phase sample, a quadrature sample, and an auxiliary sample. A CDR logic circuit processes the samples to form a timing word for each set.

Multi-mode phase-frequency detector for clock and data recovery

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San Diego, CA, United States of America

Zhi Zhu