Taiwan Semiconductor Manufacturing Comp. Ltd.

Zhi Zhong Hu

Mu-Jen Huang

Feng Zhu

Weiyang Jiang

Lin Sun

Tingting Lu

Zong-liang Cao

In some embodiments, in a method, for each array of at least a first array, a layout of the first array which comprises a plurality of cells, and a plurality of first circuit paths running across at least one side length in an array size configuration of the first array is received. Each of the plurality of cells is configured with a first node that is coupled to a respective one of the plurality of first circuit paths. A first representative characteristic associated with the plurality of first circuit paths is extracted. A universal cell model applied to each cell in a second array is generated based on a base cell model comprising parameters independent of positions in the second array, and the first representative characteristic.

Universal cell model for array and circuit simulation using the same

One or more systems and techniques for modeling are provided. An original device model, such as a SPICE model, is used as a basis for fabricating a semiconductor arrangement, such as an integrated circuit arrangement, upon a semiconductor wafer. Fabrication process variations cause measured e-parameters and measured size e-parameters of the semiconductor arrangement to vary from original design parameters of the original device model. Accordingly, a partial set of e-parameters and a partial set of size e-parameters are measured from the semiconductor arrangement, and are expanded into a full set of e-parameters and a full set of size e-parameters using e-parameter derivation and size-centric derivation. The original device model is retargeted using the full set of e-parameters and the full set of size e-parameters to create a new device model that more accurately represents the real-world or fabricated semiconductor arrangement.

Parameter modeling for semiconductor arrangements

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Shanghai, China

Zhi Zhong Hu