Globalfoundries Inc.

Advanced Micro Devices Corporation

Zhi-Yuan Wu

Juhi Bansal

Jia Feng

Ciby Thuruthiyil

Vineet Wason

Ralf Richter

Sven Beyer

Judy Xilin An

Srinath Krishnan

Jung-Suk Goo

Kevin J Yang

Sriram Balasubramanian

Lingquan Wang

Ali Icel

Stefan Duenkel

Karthik Chandrasekaran

Varsha Balakrishnan

Jochen Willi Poth

Arunima Dasgupta

Oiang Chen

Richard Yu-Kuwan Su

Sandhya Chandrashekhar

In sophisticated SOI transistor elements, the buried insulating layer may be specifically engineered so as to include non-standard dielectric materials. For instance, a charge-trapping material and/or a high-k dielectric material and/or a ferroelectric material may be incorporated into the buried insulating layer. In this manner, non-volatile storage transistor elements with superior performance may be obtained and/or efficiency of a back-bias mechanism may be improved.

Transistor element including a buried insulating layer having enhanced functionality

A method for modeling a transistor includes providing a transistor model having at least a source node, a drain node, and a gate node, simulating operation of a device using the transistor model in a computing apparatus, and generating an offset voltage at the gate node depending on a magnitude of a current passing through the device.

Modeling gate transconductance in a sub-circuit transistor model

An approach for providing sub-circuit models with corner instances for VLSI designs is disclosed. Embodiments include: determining a circuit design that includes a plurality of sub-circuit models having a plurality of characteristics; and associating, by a processor, a sub-circuit model of the plurality of sub-circuit models with a corner instance value, and another sub-circuit model of the plurality of sub-circuit models with another corner instance value. Other embodiments include analyzing, by the processor, the circuit design according to the corner instance value and the other corner instance value.

Sub-circuit models with corner instances for VLSI designs

Worst case performance of an SRAM cell may be simulated more accurately with less intensive computations. An embodiment includes determining, by a processor, a process corner G of an SRAM cell, having pull-down, pass-gate, and pull-up devices, process corner G being defined as the worst performance of the cell when only global variations of parameters of the SRAM cell are included, setting each of the pull-down, pass-gate, and pull-up devices at process corner G, performing, on the processor, a number of Monte Carlo simulations of the SRAM cell devices around process corner G with only local variations of the parameters, generating a normal probability distribution for Ibased on the local Monte Carlo simulations around process corner G, extrapolating the worst case Ifrom the normal probability distribution of Ito define a process corner SRM representing a slowest SRAM bit on a chip, and validating an SRAM cell based on the SRM corner. Embodiments further include creating a library of SRM corner values for multiple SRAM cells, and validating an SRAM cell by selecting an SRM corner from the library. Embodiments further include linearly scaling the SRM corner value with global sigma input variations from 0 sigma to 6 sigma and/or with local sigma input variations from 0 sigma to 6 sigma, selecting a scaled SRM corner value at the sigma corresponding to design and memory size requirements for the SRAM cell, simulating the scaled SRM corner by a processor, and employing the simulated scaled SRM corner to validate performance of an SRAM cell.

Model library implementation and methodology for worst case performance modeling for SRAM cells

According to one exemplary embodiment, a method for robust statistical semiconductor device modeling includes building a semiconductor device model using at least one new device parameter variation, constructing a variation library for the semiconductor device model, and verifying the variation library against measured data from physical semiconductor devices. The variation library is constructed by determining variations of the at least one new device parameter variation and standard device parameters as functions of, for example. sizes and locations of semiconductor devices on semiconductor dies.

Method for robust statistical semiconductor device modeling

According to one exemplary embodiment, a method for determining a self-heating free drain current in a transistor corresponding to a channel temperature not affected by a drain DC current includes measuring at least three unique drain currents of a transistor corresponding to at least three unique ambient temperatures. The method further includes determining at least three unique channel temperatures of the transistor corresponding to the at least three unique drain currents, thereby establishing a current-temperature relationship for the transistor. The method further includes determining the self-heating free drain current of the transistor utilizing the current-temperature relationship.

Method for determining self-heating free I-V characterstics of a transistor

According to one exemplary embodiment, a method for producing a quality assured semiconductor device model when at least one critical parameter of a semiconductor device process is upgraded includes verifying the quality assured semiconductor device model for consistency against measured data or projected targets. The method further includes verifying the quality assured semiconductor device model for accuracy and consistency when one of a number of critical parameters is varied. The method further includes verifying consistency of the quality assured semiconductor device model against an old semiconductor device model. The method further includes verifying the quality assured semiconductor device model over a range of each of a number of semiconductor device dependencies. The method further includes verifying the quality assured semiconductor device model for digital circuit operation. The method further includes verifying the quality assured semiconductor device model for analog circuit operation. The method further includes verifying convergence of the quality assured semiconductor device model.

Method for quality assured semiconductor device modeling

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Union City, CA, United States of America

Zhi-Yuan Wu