Altera Corporation

Zhi Y Wong

Paul B Ekas

Sergey Yuryevich Shumarayev

Tien Duc Pham

Leon Zheng

Shuangxia Zhu

Yongliang Lu

Siew Leong Lam

Keen Yew Loke

Albert Lee

Kia Leong Tan

Techniques and mechanisms provide a solution space visualization of bit error rates (BER) for combinations of parameter settings of transceivers. Different types of visualizations may be generated.

Transceiver parameter solution space visualization to reduce bit error rate

A phase-locked loop circuit includes phase detection circuitry to generate a first control signal based on a phase comparison between first and second periodic signals. An oscillator circuit causes a frequency of a third periodic signal to vary based on the first control signal. A frequency divider circuit divides the frequency of the third periodic signal by a frequency division value to generate a frequency of the second periodic signal. A delta sigma modulator circuit controls the frequency division value based on second control signals. First storage circuits store the second control signals based on third control signals in response to a fourth periodic signal. A second storage circuit stores an output signal based on a fourth control signal. The fourth periodic signal is generated based on the output signal of the second storage circuit.

Techniques for generating fractional periodic signals

Techniques for sampling input data streams with an integrated circuit (IC) are provided. The technique includes receiving a first input stream at a first operating rate. The first input stream is transmitted to a plurality of subsequent transceiver channels on the IC. The first input stream is then sampled at a second operating rate at each of the plurality of subsequent transceiver channels with each of the plurality of subsequent transceiver channels outputting a data stream at the second operating rate. The data stream from each of the plurality of subsequent transceiver channels is adjusted. A data stream from one of the plurality of subsequent transceiver channels is selected as an output of the IC.

Techniques for oversampling a data stream in an integrated circuit

A demultiplexer circuit separates input data having different data rates into output data. A phase-locked loop circuit generates first clock signals having average frequencies that are based on a frequency of a second clock signal times a fractional, non-integer number. A serializer circuit serializes a set of the output data to generate serial data signals in response to one of the first clock signals generated by the phase-locked loop circuit.

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San Jose, CA, United States of America

Zhi Y Wong