Micron Technology Incorporated

Delta Electronics (shanghai) Co., Ltd

Delta Electronics, Inc.

Other

Magsonder Innovation (shanghai) Co., Ltd.

Zhi Qi Huang

Wei Lu Chu

Dong Pan

Jiang Chu

Wei Zhu Chen

Hiromasa Noda

Hiroshi Akamatsu

Wei Zhang

Zeng Li

Yi-Fan Wu

I-Chi Cheng

Juming Hu

Han Zhang

Johnson Li

C S Kung

Yuetao Duan

Guilin Jiang

An amplifier includes a first stage and a second stage. The first stage includes a floating current source to maintain current within a threshold. The first stage also includes a local common mode feedback configured to provide gain to an input signal. Moreover, the second stage includes a driver that provides a load current to a load coupled to the amplifier.

Low power VB class AB amplifier with local common mode feedback

A memory device includes a voltage generator configured to generate a reference voltage for transmission to at least one component of the memory device. The voltage generator includes a first input to receive a first signal having a first voltage value. The voltage generator also includes a second input to receive a second signal having a second voltage value. The voltage generator further includes a first circuit configured to generate third voltage and a second circuit coupled to the first circuit to receive the third voltage value, wherein the second circuit receives the first signal and the second signal and is configured to utilize the third voltage value to facilitate comparison of the first voltage value and the second voltage value to generate an output voltage.

Amplifier input pair protection

Methods, systems, and devices for operating an amplifier with a controllable pull-down capability are described. A memory device may include a memory array and a power circuit that generates an internal signal for components in the memory array. The power circuit may include an amplifier and a power transistor that is coupled with the amplifier. A pull-down capability of the amplifier may be controllable using an external signal that is based on a difference between a reference signal and the internal signal. The power circuit may also include a comparator that is coupled with the amplifier and configured to compare the reference signal and the internal signal. Components of the comparator may be integrated with components of the amplifier, may share a bias circuit, and may use nodes within the amplifier to control the comparator. A signal output by the comparator may control the pull-down capability of the amplifier.

Amplifier with a controllable pull-down capability for a memory device

Methods, systems, and devices for timing signal delay compensation in a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous relative to an input signal. To support asynchronous timing, a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. In accordance with examples as disclosed herein, a memory device may include delay components having a variable and configurable impedance, where the configurable impedance may be based at least in part on a configuration signal generated at the memory device. A configuration signal may be generated based on fabrication characteristics of the memory device, or based on operating conditions of the memory device, or various combinations thereof.

Timing signal delay compensation in a memory device

An inductor magnetic core and an inductor using the same are disclosed. The inductor magnetic core includes a middle column, an upper yoke, a lower yoke, and at least two high magnetically-permeable side columns. The middle column is disposed between a middle part of the upper yoke and a middle part of the lower yoke, a coil is wound the middle column, and a saturation magnetic flux density of the middle column is higher than that of the upper yoke and the lower yoke. The at least two high magnetically-permeable side columns are disposed in interval between the upper yoke and the lower yoke, and two ends of each high magnetically-permeable side column are connected to outer edges of the upper yoke and the lower yoke, respectively. The inductor magnetic core and the inductor of the present invention improves utilization of the yoke, and also provide compact structure and simple production.

Inductor magnetic core and inductor using the same

Devices for generating a delay output signal are disclosed. A device may include a first delay circuit and a second delay circuit coupled in series between a first node and a second node in a delay path for the device, and having a third node therebetween. The device may also include a third circuit coupled to the third node and configured to charge the third node responsive to detecting a signal has passed through the first node and the third node. Associated semiconductor devices and methods are also disclosed.

Delay circuits, and related semiconductor devices and methods

Methods, systems, and devices for timing signal delay for a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous relative to an input signal. To support asynchronous timing, a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. A memory device may include delay components having a configurable impedance based at least in part on one or more fabrication characteristics of the memory device, one or more operating conditions of the memory device, one or more bias voltages, or a combination thereof.

Timing signal delay for a memory device

An electronic device includes a first input that receives an input signal when the electronic device is in operation, a long L gate comprising a long L transistor, a first activation transistor coupled to a gate of the long L transistor, and a second activation transistor coupled to the gate of the long L transistor. The electronic device also includes a switch directly coupled to a second input of the long L gate, a path directly coupled to a first output of the long L gate, a capacitor coupled to the path, and a second output that when in operation transmits an output signal as a delayed signal with respect to the input signal.

Delay circuitry with reduced instabilities

Methods and apparatus for generating a delayed output signal from an input signal applied to an RC delay circuit of a semiconductor device during an active mode. The RC delay circuit is configured to pull up a voltage level on a node responsive to a reset signal during a stand-by mode.

Semiconductor device, delay circuit, and related method

Apparatus and methods are described for voltage dependent delay. An example apparatus includes an oscillator including a delay circuit that is configured to provide an oscillating output signal has a delay based on a delay of the delay circuit. The delay of the delay circuit is based on a voltage it receives. For example, the delay of the delay circuit increases for an increasing received voltage and decreases for a decreasing received voltage. As a result, the oscillating output signal provided by the oscillator is based on the received voltage. For example, a frequency of the oscillating output signal decreases for increasing received voltage and increases for decreasing received voltage. Described in another way, the frequency of the oscillating output signal is relatively low for relatively high received voltage and relatively high for relatively low received voltage.

Apparatuses and methods for voltage dependent delay

A memory device includes a memory array including a plurality of memory cells; and an array timer coupled to the memory array, configured to generate an output timing signal based on a fixed input and a reference signal, wherein: the fixed input is from a supply circuit, the reference signal is from a reference block, and the output timing signal is configured to control the memory array.

Memory device with an array timer mechanism

A memory device includes a memory array including a plurality of memory cells; and an array timer coupled to the memory array, configured to generate an output timing signal based on a V-I stable input and an analog reference signal, wherein: the V-I stable input is from a bandgap supply circuit, the analog reference signal is from an analog reference block, and the output timing signal is configured to control the memory array.

The present invention discloses a power inductor encapsulated through injection molding. The power inductor comprises a coil winding, a soft magnetic ferrite middle column inserted in a middle of the coil winding, and a magnetic powder glue for encapsulating the coil winding and the soft magnetic ferrite middle column through injection molding. The power inductor is square and meets L&#x2265;W and 2rc&#x3e;0.4&#xd7;W, wherein a section width of the soft magnetic ferrite middle column perpendicular to a height direction of the inductor is 2rc, a length of the power inductor isL, and a width of the power inductor isW. According to the present invention, a balanced direct-current resistance and a direct-current superposition saturation characteristic can be obtained, and the direct-current resistance is greatly decreased while an excellent direct-current superposition saturation characteristic is ensured.

Power inductor encapsulated through injection molding

The present application discloses a three-phase reactor, including: an upper yoke and a lower yoke, the upper yoke and the lower yoke containing a first material; and at least three first core columns, the first core columns containing a second material, and the both ends of each of the first core columns being connected with the upper yoke and the lower yoke, respectively, wherein, the relative permeability of the first material is greater than that of the second material, and at least one air gap is positioned in each of the first core columns. In the three-phase reactor proposed by the present disclosure, the yokes are made of a material different from that of the core columns, and air gaps are positioned in the core columns, so that the eddy current losses may be reduced significantly and the requirement for the use of high power may be satisfied.

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Shanghai, China

Zhi Qi Huang