National Changhua University of Education

National Changua University of Education

Zhi-Ming Lin

An ADC with comparing circuit units is provided. Each comparing circuit unit comprises a first resistor, a second resistor, and a CMOS. The first and second resistors provide first and second level voltages, respectively. The base of the PMOS is electrically connected to the power source and the base of the NMOS is connected to the source of the NMOS. The signal input port is located at the gate of the CMOS and receives an analog signal. The first level port of the CMOS is located at the source of the NMOS and receives the first level voltage. The second level port of the CMOS is located at the source of the PMOS and receives the second level voltage. The signal output port of the CMOS is located at the drain and outputs a digital signal.

Analog-to-digital converter (ADC) and comparator unit thereof

A non-linear transient analysis module and method for phase locked loop (PLL) is disclosed. The method includes a pulse cycle defined by the larger period of two input frequencies; a pulse width defined by the accumulation value of period difference. Each pulse cycle is divided into two linear regions, a first voltage at the beginning of the pulse cycle as an initial value then applying a first linear equation to obtain a second voltage, and then the second voltage as an initial value then applying a second linear equation to obtain a third voltage which is used to be an initial value for next pulse cycle. An average voltage of the first region and the second region is inputted into the VCO to generate an output as the PFD input. The aforementioned steps are repeated to complete a simulation of PLL transient response.

Growing community of inventors

Changhua, Taiwan

Zhi-Ming Lin