Xilinx, Inc.

Other

Zhi-min Ling

Robert W Wells

Jae Cho

Yuezhen Fan

Shahin Toutounchi

Robert D Patrie

Xiao-Yu Li

Eric Thorne

David Mark

Vincent L Tong

Feng Wang

Joe W Zhao

David M Mahoney

Yuhao Luo

Xin X Wu

Anthony P Calderone

Arnold Abrera Cruz

Tarek Eldin

Stephen Wing-Ho Tang

Shelly G Davis

Clay S Johnson

Jason Xu

The present disclosure relates generally to a method to break and assemble solar cells to make solar panel. The present disclosure provides a method to produce solar pieces from solar cell, as well as assemble them together. The present disclosure device is unique when compared with other known devices and solutions because the present disclosure provides a high speed method to break scribed cells into pieces. A method of forming a string of solar cells includes providing a scribe line on a solar cell and placing a first ribbon on the solar cell. The method then includes placing the solar cell on a supporter and then breaking the solar cell into a plurality of solar cell pieces. The method then has the step of placing a second ribbon on the solar cell pieces and soldering the first and second ribbons and the solar cell pieces and then assembling the solar cell pieces into a string of solar cells.

Method to break and assemble solar cells

A test methodology for testing a memory device with a RSR feature is disclosed. For example, a method for testing a memory device having at least one memory cell group, at least one redundant memory cell group, and a defect detect register is disclosed. In one embodiment, the method applies at least one memory test to the at least one memory cell group; and applies a defect detect register test to the defect detect register.

Method and apparatus for testing a memory device with a redundant self repair feature

The configuration of a faulty line segment in a switch matrix of a programmable logic device is identified using read-back capture. Each original programmable interconnection point ('PIP') in the line segment is tested by generating routes from a first logic port through the original line segment and PIP, through all PIPs, adjacent to the original PIP to the opposite logic port. Routes through all PIPs adjacent to the PIPs in the line segment from the first logic port to the second logic port, and from the second logic port to the first logic port, are tested to isolate the fault in the line segment.

Method of automatic fault isolation in a programmable logic device

The embodiments of the present invention enable a new metal diagnosis pattern based on a production test pattern to quickly identify open and short circuits of metal lines which cannot be probed, such as the long lines of a programmable logic device, and to further isolates the fault location for physical failure analysis. According to one aspect of the invention, a circuit locally drives a plurality of metal long line segments to determine whether a defect in a line is a short circuit, or further to identify the location of an open circuit.

Test circuit for and method of identifying a defect in an integrated circuit

Described are methods and circuits for identifying defective device layers and localizing defects. Production PLD tests extract statistically significant data relating failed interconnect resources to the associated conductive metal layer. Failure data thus collected is then analyzed periodically to identify layer-specific problems. Test circuits in accordance with some embodiments employ interconnect resources heavily weighted in favor of specific conductive layers to provide improved layer-specific failure data. Some such test circuits are designed to identify open defects, while others are designed to identify short defects.

Method and circuits for localizing defective interconnect resources in programmable logic devices

Methods for monitoring and improving the fabrication process of integrated circuits using configurable devices are described. In one aspect, the method includes instantiating a test pattern on one or more configurable devices fabricated using the fabrication process, identifying an underperforming region of the configurable devices, and determining if the underperforming region is layout sensitive. At least one of the fabrication process and the layout of the configurable device can then be adjusted based on the determination. In some embodiments, the configurable device may be a programmable logic device, such as a field programmable logic array.

Method for monitoring and improving integrated circuit fabrication using FPGAs

Method and apparatus are disclosed for analyzing defect data produced in testing a semiconductor chip from a logic design. In various embodiments, input for processing is a first inspection data set that identifies a first set of physical locations that are associated with defects detected during fabrication of the chip. Also input is a second test data set that includes one or more identifiers associated with failing circuitry in the chip. A second set of physical locations is determined from the one or more identifiers of failing circuitry, hierarchical relationships between blocks of the design, and placement information associated with the blocks. Each of the one or more identifiers is associated with at least one of the blocks. Correspondences are identified between physical locations in the first inspection data set and the second set of physical locations.

Correlation of electrical test data with physical defect data

Disclosed are methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user's design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given user's design without requiring the PLD vendor to understand the user's design.

Application-specific testing methods for programmable logic devices

FPGAs that contain at least one localized defect may be used to implement some designs if the localized defect is not used in the designs. To determine if the FPGA is suitable to implement a design, the design is loaded into the FPGA. The FPGA is tested to determine whether it can execute the design accurately even with the localized defect. The FPGA will be marked as suitable for that design if it passes the test. If the FPGA is found to be unsuitable for one design, additional designs may be tested. Thus, a FPGA manufacturer can sell FPGAs that are normally discarded. As a result, the price of these FPGAs could be set significantly low.

Method of using partially defective programmable logic devices

A new testing method uses a field programmable gate array to emulate faults, instead of using a separate computer to simulate faults. In one embodiment, a few (e.g., two or three) known good FPGAs are selected. A fault is introduced into the design of a FPGA configuration. The configuration is loaded into the FPGAs. A test vector is applied and the result is evaluated. If the result is different from that of a fault-free configuration, the fault is caught. One application of this method is to evaluate fault coverage. A fault model that can be used in the present invention is disclosed.

Fault emulation testing of programmable logic devices

A reticle that is modified to prevent bridging of the masking material (e.g., chrome) between portions of the lithographic mask pattern during an integrated circuit fabrication process. According to a first aspect, the modification involves electrically connecting the various portions of the lithographic mask pattern that balance charges generated in the portions during fabrication processes. In one embodiment, sub-resolution wires that extend between the lithographic mask pattern portions facilitate electrical conduction between the mask pattern portions, thereby equalizing dissimilar charges. In another embodiment, a transparent conductive film is formed over the lithographic mask pattern to facilitate conduction. In accordance with a second aspect, the modification involves separating the various portions of the lithographic mask pattern into relatively small segments by providing sub-resolution gaps between the various portions, thereby minimizing the amount of charge that is generated on each portion.

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Cupertino, CA, United States of America

Zhi-min Ling