Crossbar, Inc.

Future Wei Technologies, Inc.

Huawei Technologies Co., Limited

Zhi Li

Sung Hyun Jo

Hagop A Nazarian

Sang Thanh Nguyen

Tanmay Kumar

Jeremy Guy

Xiangyang Xu

Guangyu Shi

Sung-Hyun Jo

Derek Lau

Jordan Frick

Improved erase techniques and apparatuses can improve performance and longevity of non-volatile memory. Various disclosed techniques include performing an erase operation(s) on a group of such memory cells, followed by a weak program operation. One or more subsequent erase-verify operations can be implemented until no erase disturb states are detected for the memory cells, or until a maximum erase-verify cycle count is reached. In one or more embodiments, additional weak program and erase-verify cycles can be implemented to enhance cycle longevity and reduce erase disturb states for the group of non-volatile memory.

Erase algorithm with a weak program pulse for non-volatile memory

Techniques for using native and/or previously programmed resistive switching devices as one time programmable memory are discussed. On example method comprises allocating a set of resistive switching devices to be one time programmable memory; determining data to be stored in the set of resistive switching devices; for each resistive switching device of the set of resistive switching devices, assigning one of a first digital value or a second digital value to that resistive switching device, based on the data; and for each resistive switching device assigned the first digital value, permanently programming that resistive switching device via reverse formation.

Reverse programmed resistive random access memory (RAM) for one time programmable (OTP) applications

Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications.

Distinct chip identifier sequence utilizing unclonable characteristics of resistive memory on a chip

Two-terminal memory can be set to a first state (e.g., conductive state) in response to a program pulse, or set a second state (e.g., resistive state) in response to an erase pulse. These pulses generally provide a voltage difference between the two terminals of the memory cell. Certain electrical characteristics associated with the pulses can be manipulated in order to enhance the efficacy of the pulse. For example, the pulse can be enhanced or improved to reduce power-consumption associated with the pulse, reduce a number of pulses used to successfully set the state of the memory cell, reduce wear or damage to the memory cell, or to improve Ion or Ioff distribution associated with changing the state of the memory cell.

Enhanced erasing of two-terminal memory

Two-terminal memory can be set to a first state (e.g., conductive state) in response to a program pulse, or set a second state (e.g., resistive state) in response to an erase pulse. These pulses generally produce a voltage difference between the two terminals of the memory cell. Certain electrical characteristics associated with the pulses can be manipulated in order to enhance the efficacy of the pulse. For example, the pulse can be enhanced or improved to reduce power-consumption associated with the pulse, reduce a number of pulses used to successfully set the state of the memory cell, or to improve Ion distribution associated with active metal particles included in the memory cell.

Enhanced programming of two-terminal memory

A server configured to form part of a data protection group, wherein the server comprises a memory, a transceiver configured to receive a request to store a data file from another device, and a processor coupled to the memory and the transceiver and configured to acquire the request to store a data file, write the data file to a container in the memory, and encode the container contents when the container becomes full to generate a plurality of encoded blocks, wherein the transceiver is further configured to distribute the plurality of encoded blocks over peer servers in the data protection group.

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Santa Clara, CA, United States of America

Zhi Li