Caelus Technologies Limited

Zhi Jun Li

Chi Fung Lok

Xiaoyong He

An N-channel interleaved Analog-to-Digital Converter (ADC) has a variable delay added to each ADC's input sampling clock. The variable delays are each programmed by a Successive-Approximation-Register (SAR) during calibration to minimize timing skews between channels. In each channel the ADC output is filtered, and a product derivative correlator generates a product derivative factor for correlation to two adjacent ADC channels. A matrix processor arranges the product derivative factors from the product derivative correlators into a matrix that is multiplied by a correlation matrix. The correlation matrix is a constant generated from an N&#xd7;N shift matrix. The matrix processor outputs a sign-bit vector. Each bit in the sign-bit vector determines when tested SAR bits are set or cleared to adjust a channel's variable delay. Sampling clock and component timing skews are reduced to one LSB among all N channels.

Matrix processor generating SAR-searched input delay adjustments to calibrate timing skews in a multi-channel interleaved analog-to-digital converter (ADC)

An N-channel interleaved Analog-to-Digital Converter (ADC) has a variable delay added to each ADC's input sampling clock. The variable delays are each programmed by a Successive-Approximation-Register (SAR) during calibration to minimize timing skews between channels. An auto-correlator generates a sign of a correlation error for a pair of ADC digital outputs. SAR bits are tested with the correlation sign bit determining when to add or subtract SAR bits. First all pairs are calibrated in a first level of a binary tree of mux-correlators. Then skews between remote pairs and groups are calibrated in upper levels of the binary tree using auto-correlators with inputs muxed from groups of ADC outputs input to the binary tree of mux-correlators. The binary tree of mux-correlators can include bypasses for odd and non-binary values of N. Sampling clock and component timing skews are reduced to one LSB among both adjacent channels and remote channels.

Calibration of timing skews in a multi-channel interleaved analog- to-digital converter (ADC) by auto-correlation of muxed-together channels in binary output tree

A first calibration measures capacitor array mis-match and updates a Look-Up Table (LUT) with calibrated weights that are copied to both a positive LUT and a negative LUT, and then adjusted for non-linearity errors by a second calibration using a Least Mean-Square (LMS) method. The binary code in the Successive-Approximation Register (SAR) is complemented to generate a complement code with a sign bit. When the sign bit is positive, entries for complement code bits=1 are read from the positive LUT and summed, a first offset added, and the sum normalized to get a corrected code. When the sign bit is negative, entries for complement code bits=0 are read from the negative LUT and summed, a second offset added, and the sum normalized to get the corrected code. A Multi-Variable Stochastic Gradient Descent method generates polynomial coefficients that further correct the corrected code.

Calibration of residual errors using least-mean-squares (LMS) and stochastic-gradient methods for an analog-to-digital converter (ADC) with a pre-calibrated lookup table

Growing community of inventors

Guangzhou, China

Zhi Jun Li